System Error Enable (Sere) Bit 8; Fast Back-To-Back Capable (Fbbc) Bit 23; Data Parity Reported (Dpr) Bit 24; Devsel Timing (Dst1-Dst0) Bits 26 And 25 - Motorola DSP56305 User Manual

6.6.8.5

System Error Enable (SERE) Bit 8

The SERE bit is used to enable the HSERR signal driving by the HI32, when in the PCI
mode (HM = $1). If SERE is cleared, the HSERR signal disabled (i.e. high impedance). If
SERE is set: if the force system error (SERF) bit in the DPCR is set and the HI32 is an
active PCI agent, or an address parity error was detected, the HI32 pulses the HSERR
signal and sets the signalled system error (SSE) bit in the CSTR.
The personal hardware reset clears SERE.
6.6.8.6

Fast Back-to-Back Capable (FBBC) Bit 23

The FBBC indicates the HI32 supports fast back-to-back transactions as a target, when in
the PCI mode (HM=$1). This bit is hardwired to one.
6.6.8.7

Data Parity Reported (DPR) Bit 24

The DPR indicates the data parity error detected, when in the PCI mode (HM=$1). The
DPR is set if the HI32 acts as a bus master and detects a data parity error or samples
HPERR asserted while PERR bit is set in CCMR. The DPR bit is cleared when it is written
with one by the host processor.
The personal hardware reset clears DPR.
6.6.8.8

DEVSEL Timing (DST1-DST0) Bits 26 and 25

The DST1-DST0 bits encode the timing of the HDEVSEL signal, when in the PCI mode
(HM=$1). These bits are hardwired to DST = $1, indicating that the HI32 belongs to the
'medium DEVSEL timing' class of the PCI devices.
6.6.8.9

Signaled Target Abort (STA) Bit 27

The STA indicates a target-abort PCI bus event has been generated. When in the PCI
mode (HM=$1) and the HI32, as a target device, terminates a transaction with
target-abort, the STA is set. The STA bit is cleared when it is written with one by the host
processor.
The personal hardware reset clears STA.
6.6.8.10

Received Target Abort (RTA) Bit 28

The RTA indicates a target-abort PCI bus event has been generated. When in the PCI
mode (HM=$1) and the HI32, as a master device, detects that its transaction is
terminated with target-abort, the RTA is set. The RTA bit is cleared when it is written
with one by the host processor.
The personal hardware reset clears RTA.
MOTOROLA DSP56305 User's Manual
HOST INTERFACE (HI32)
HOST SIDE Programming Model
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