Motorola DSP56305 User Manual page 27

Figure 1-1 DSP56305 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
Figure 2-1 Signals Identified by Functional Group . . . . . . . . . . . . . . . . . . . . . . . 2-4
Figure 2-2 Host Interface/Port B Detail Signal Diagram . . . . . . . . . . . . . . . . . . . 2-5
Figure 3-1 Default Memory Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Figure 3-2 Instruction Cache Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
Figure 3-3 Memory Switch Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Figure 3-4 Memory Switch Enabled, Instruction Cache Enabled . . . . . . . . . . . 3-15
Figure 3-5 Sixteen-Bit Compatibility Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
Figure 3-6 Sixteen-Bit Compatibility Mode, Instruction Cache Enabled . . . . . . 3-17
Figure 3-7 Sixteen-Bit Compatibility Mode, Memory Switch Enabled. . . . . . . . 3-18
Figure 3-8 Sixteen-Bit Compatibility Mode, Memory Switch Enabled,
Instruction Cache Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
Figure 4-1 Interrupt Priority Register C (IPR-C) (X:$FFFFFF) . . . . . . . . . . . . . 4-16
Figure 4-2 Interrupt Priority Register P (IPR-P) (X:$FFFFFE) . . . . . . . . . . . . . 4-17
Figure 4-3 DSP56305 Operating Mode Register (OMR) . . . . . . . . . . . . . . . . . 4-23
Figure 4-4 PLL Control Register (PCTL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
Figure 4-5 Identification Register Configuration
(DSP56305 Revision 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24
Figure 4-6 JTAG Identification Register Configuration (Revision 0) . . . . . . . . . 4-25
MOTOROLA
LIST OF FIGURES
DSP56305 User's Manual xxv