From The Essi; Essi Transmit 2 Enable (Te2) Crb Bit 14 - Motorola DSP56305 User Manual

Enhanced Synchronous Serial Interface (ESSI)
ESSI Programming Model
7.4.2.13 Enabling and Disabling Data Transmission from the ESSI
The ESSI has three Transmit Enable bits (TE[2:0]), one for each data transmitter. The
process of transmitting data from TX1 and TX2 is the same. TX0 can also operate in
Asynchronous mode. The normal transmit enable sequence is to write data to one or
more Transmit Data Registers (or the Time Slot Register (TSR) before setting the TE bit.
The normal transmit disable sequence is to set the Transmit Data Empty (TDE) bit, then
clear the TE, Transmit Interrupt Enable (TIE), and Transmit Exception Interrupt Enable
(TEIE) bits. In the Network mode, clearing the appropriate TE bit and setting it again
disables the corresponding transmitter (0, 1, or 2) after transmission of the current data
word. The transmitter remains disabled until the beginning of the next frame. During
that time period, the corresponding SC (or STD in the case of TX0) signal remains in the
high-impedance state.
7.4.2.14

ESSI Transmit 2 Enable (TE2) CRB Bit 14

The TE2 bit enables the transfer of data from TX2 to Transmit Shift Register 2. TE2 is
functional only when the ESSI is in Synchronous mode and is ignored when the ESSI is
in Asynchronous mode.
When TE2 is set and a frame sync is detected, the transmitter 2 is enabled for that frame.
When TE2 is cleared, transmitter 2 is disabled after completing transmission of data
currently in the ESSI Transmit Shift Register. Any data present in TX2 is not transmitted.
If TE2 is cleared, data can be written to TX2; the TDE bit will be cleared, but data will not
be transferred to Transmit Shift Register 2.
Keeping the TE2 bit cleared until the start of the next frame causes the SC1 signal to act
as serial I/O flag from the start of the frame, in both Normal and Network mode. The
On-demand mode transmit enable sequence can be the same as the Normal mode, or the
TE2 bit can be left enabled.
The TE2 bit is cleared by either a hardware reset signal or a software reset instruction.
The setting of the TE2 bit does not affect the generation of frame sync or
Note:
output flags.
7-28 DSP56305 User's Manual MOTOROLA