Transmit Request Enable (Treq) Bit 1 - Motorola DSP56305 User Manual

HOST INTERFACE (HI32)
HOST SIDE Programming Model
In PCI mode (HM = $1) memory space transactions, the HCTR is accessed if the PCI
address is HI32_base_address: $010.
The HCTR is written in accordance with the byte enables (HC3/HBE3-HC0/HBE0
signals). Byte lanes that are not enabled are not written and the corresponding bits
remain unchanged.
The HCTR bits affect the HI32 logic upon the completion of the transaction in they were
written.
When in a Universal Bus mode (HM=$2 or $3), the HCTR is accessed if the HA10-HA3
value matches the HI32 base address (CBMA, see Section 6.6.11) and the HA2-HA0
value is $4.
The control bits are described in the following paragraphs.
6.6.1.1

Transmit Request Enable (TREQ) Bit 1

The TREQ bit is used to control the HIRQ and HDRQ signals for host transmit data
transfers (see Table 6-13), when in a Universal Bus mode (HM=$2 or $3).
If DMA enable bit (DMAE) is cleared, TREQ enables the host interrupt request HIRQ
signal when the host transmit data request (HTRQ) status bit in the HI32 status register
(HSTR) is set. If TREQ is cleared, HTRQ host interrupt requests are disabled. If TREQ is
set, the host interrupt request HIRQ signal will be asserted if HTRQ is set. HDRQ is
deasserted.
If DMAE is set, TREQ enables the host DMA request (HDRQ) signal when the host
transmit data request (HTRQ) status bit in the HSTR is set. If TREQ is cleared, HTRQ
external DMA requests are disabled. If TREQ is set, the host DMA request HDRQ signal
will be asserted if HTRQ is set. HIRQ is deasserted (high impedance if HIRD = 0 in the
DCTR).
The personal hardware reset clears TREQ.
MOTOROLA DSP56305 User's Manual 6-55