Timer Pulse (Mode 1) - Motorola DSP56305 User Manual

Timer/Event Counter
Timer Modes of Operation
9.4.1.2

Timer Pulse (Mode 1)

Bit Settings
TC3 TC2 TC1
0 0 0
In this mode, the timer generates an external pulse on its TIO signal when the timer
count reaches a pre-set value.
Set the TE bit (TCSR Bit 0) to clear the counter and enable the timer. Load the timer count
value into the TCPR. The counter is loaded with the TLR value when the first timer clock
signal is received. The timer clock signal can be taken from either the DSP56300 clock
divided by two (CLK/2) or from the prescaler clock output. Each subsequent timer clock
signal increments the counter.
When the counter value equals the TCPR value, the TCF bit (TCSR Bit 21) is set, and if
the TCIE bit (TCSR Bit 2) is set, a compare interrupt is generated. Also, a TIO pulse with
width equal to the timer clock period is output. The TIO signal polarity is determined by
the value of the INV bit (TCSR Bit 8). On the next timer clock signal, if the TRM bit
(TCSR Bit 9) is set, the counter is reloaded with the TLR value and the count is resumed;
but if the TRM bit is cleared, the counter continues to be incremented on each timer clock
signal.
This process is repeated until the timer is disabled (i.e., until the TE bit is cleared). If the
counter overflows, the TOF bit (TCSR Bit 20) is set, and if the TOIE bit (TCSR Bit 1) is set,
an overflow interrupt is generated. The counter contents can be read at any time by
reading the TCR.
The TLR value sets the delay between starting the timer and generating the output pulse.
To generate successive output pulses with a delay of X clocks between signals, set the
TLR value to X/2 and set the TRM bit.
Note: The TIO bit polarity is dependent on the INV bit value. When TE is set, the
TIO signal output value is put equal to the INV bit value to guarantee the first
signal transition is correct.
9-20
TC0 TIO Clock
1 Output Internal
DSP56305 User's Manual
Mode Characteristics
# KIND
1 Timer
NAME
Pulse
MOTOROLA