Host Flags (Hf2-Hf0) Bits 5-3; Hi32 Active (Hact) Bit 23; Dsr Reserved Status Bits 22-6 - Motorola DSP56305 User Manual

6.5.5.4

Host Flags (HF2-HF0) Bits 5-3

The HF2-HF0 bits in the DSR indicate the state of host flags HF2-HF0 respectively, in the
host control register (HCTR) on the host side. HF2-HF0 can only be changed, albeit
indirectly, by the host processor.
In the PCI mode (HM = $1) the HF2-HF0 bits are updated at the end of a transaction.
Note: A potential problem exists when reading the status bits HF2-HF0 as an
encoded triad. During personal hardware reset these bits are cleared
asynchronously. For example: If HF2-HF0 change from 111 to 000, there is a
small probability the DSP56300 core could read the bits during transition and
receive 001 or 110 or other combinations instead of 000. This problem can be
avoided if the DSP56300 core reads these bits twice and checks for consensus.
The personal hardware reset clears HF2-HF0.
6.5.5.5

HI32 Active (HACT) Bit 23

The HACT bit indicates the activity of the HI32. The HACT is cleared in response to
HM=$0 (Terminate and Reset) and set by HM = $1, $2, $3, $5.
HACT is cleared in response to Terminate and Reset (HM = $0):
• If HM = $0 is written (Terminate and Reset), while the HI32 is an active PCI bus
master or selected target in a memory space transaction, a master initiated
termination or target disconnect, respectively, is generated. When the PCI idle
state is detected, the HACT status bit in the DSR is cleared.
• If HM = $0 is written (Terminate and Reset), while the HI32 is in a Universal Bus
or Self Configuration mode (HM = $2, $3 or $5), the HACT status bit in the DSR is
cleared immediately.
When HACT is set, the HI32 is active, and the DCTR mode and polarity bits must NOT
be changed.
Hardware and software resets clear HACT.
6.5.5.6

DSR Reserved Status Bits 22-6

These bits are reserved for future expansion and read as zeros.
MOTOROLA DSP56305 User's Manual
HOST INTERFACE (HI32)
DSP SIDE Programming Model
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