Motorola DSP56305 User Manual page 644

PROGRAMMING REFERENCE
HI32 Registers - Quick Reference (Sheet 2 of 8)
Reg Bit #
Mnemonic Name
DPCR MTIE
MRIE
MAIE
PEIE
TAIE
TTIE
TCIE
CLRT
MTT
SERF
18 MACE
MWSD
RBLE
IAE
D-44
Master Transmit Interrupt
Enable
Master Receive Interrupt
Enable
Master Address Interrupt
Enable
Parity Error Interrupt Enable 0
Transaction Abort Interrupt
Enable
Transaction Termination Int.
En.
Transfer Complete Interrupt
Enable
Clear Transmitter
Master Transfer Terminate
HSERR Force
Master Access Counter
Enable
Master Wait State Disable
Receive Buffer Lock Enable 0
Insert Address Enable
DSP56305 User's Manual
Val Function
0 MTRQ interrupt disabled
1 MTRQ interrupt enabled
0 MRRQ interrupt disabled
1 MRRQ interrupt enabled
0 A/DPER interrupt disabled
1 A/DPER interrupt enabled
MARQ interrupt disabled
1 MARQ interrupt enabled
0 M/TAB interrupt disabled
1 M/TAB interrupt enabled
0 TO/DIS/RTY interrupt disabled
1 TO/DIS/RTY interrupt enabled
0 HDTC interrupt disabled
1 HDTC interrupt enabled
0 inactive
1 empty master transmitter path
0 inactive
1 terminate current PCI
transaction
0 inactive
1 generate a PCI system error
0 unlimited burst length
1 burst length is limited by the BL
value
0 HI32 master inserts wait states
1 HI32 master releases bus
HI32 responds to new
accesses
1 HI32 retries accesses after
write accesses
0 HI32 does not insert address
1 HI32 inserts address in
incoming data
Comments Reset Type
HS PH
0 -
0 -
0 -
0 -
0 -
0 -
0 -
may be set 0 -
only if MARQ
= 1
cleared by
hardware
may be set 0 -
only if MWS =
1
cleared by
hardware
cleared by 0 -
hardware
0 -
may be set 0 -
only if MARQ
= 1
may be 0 -
changed only
in PS reset
may be 0 -
changed only
in PS reset
MOTOROLA
PS
-
-
-
-
-
-
-
-
-
-
-
-
-
-