Timer Reload Mode (Trm) — Tcsr Bit 9 - Motorola DSP56305 User Manual

Timer/Event Counter
Timer Architecture
Table 9-3 Inverter (INV) Bit Operation (Continued)
TIO Programmed as Input
Mode
INV = 0
Event is captured
6
on the rising edge
of the signal from
the TIO signal
7 —
9 —
10 —
The INV bit is cleared by a hardware RESET signal or a software RESET instruction.
Note: The INV bit affects both the timer and GPIO modes of operation. To ensure
correct operation, this bit should be changed only when one or both of the
following conditions is true:
• The timer has been disabled by clearing the TE bit in the TCSR.
• The timer is in GPIO mode.
The INV bit does not affect the polarity of the prescaler source when the TIO is used as
input to the prescaler.
9.3.3.6 Timer Reload Mode (TRM) — TCSR Bit 9
The Timer Reload Mode (TRM) bit controls the counter preload operation.
If the TRM bit is set:
• In Timer (0–3) and Watchdog (9–10) modes, the counter is reloaded each time
after it reaches the value contained by the TCPR. Initially, the counter is
preloaded with the TLR value after the TE bit is set and the first internal or
external clock signal is received.
9-14
INV = 1
Event is captured
on the falling
edge of the signal
from the TIO
signal
— Pulse generated
by the timer has
positive polarity
— Pulse generated
by the timer has
positive polarity
— Pulse generated
by the timer has
positive polarity
DSP56305 User's Manual
TIO Programmed as Output
INV = 0 INV = 1
—
Pulse generated by
the timer has
negative polarity
Pulse generated by
the timer has
negative polarity
Pulse generated by
the timer has
negative polarity
—
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