Table 6-6 Dsp Pci Control Register (Dpcr) - Motorola DSP56305 User Manual

6.5.2 DSP PCI Control Register (DPCR)
11 10 9
TTIE
23 22 21
IAE
* - Reserved, read as zero and should be written with zero.
Bit
1
2
4
5
7
9
12
14
15
16
18
19
20
21
23-22,17,13,
11-10,8,6,3,0
The DPCR is a 24-bit read/write control register used by the DSP56300 core to control
the HI32 PCI interrupts, and interface logic. The DPCR cannot be accessed by the host
processor. All reserved bits are read as zeros and should be programmed as zeros for
future compatibility. The bit manipulation instructions are useful for accessing
individual bits in the DPCR. The DPCR bits are described in the following paragraphs.
MOTOROLA

Table 6-6 DSP PCI Control Register (DPCR)

8 7 6
TAIE
20 19 18
RBLE MWSD MACE
Name
MTIE Master Transmit Interrupt Enable
MRIE Master Receive Interrupt Enable
MAIE Master Address Interrupt Enable
PEIE Parity Error Interrupt Enable
TAIE Transaction Abort Interrupt Enable
TTIE Transaction Termination Interrupt Enable
TCIE Transfer Complete Interrupt Enable
CLRT Clear Transmitter
MTT Master Transfer Terminate
SERF HSERR Force
MACE Master Access Counter Enable
MWSD Master Wait State Disable
RBLE Receive Buffer Lock Enable
IAE Insert Address Enable
reserved
DSP56305 User's Manual
HOST INTERFACE (HI32)
DSP SIDE Programming Model
5 4 3
PEIE MAIE
17 16 15
SERF MTT
Function
2 1 0
MRIE MTIE
14 13 12
CLRT TCIE
6-21