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VITERBI CO-PROCESSOR
Programming Model
DECEN, and EQEN in VCRA are not cleared by the internal logic. The CME bit should
be changed only when VCOP is in the VCOP individual reset state.
13.5.4.4
Data Mode (HD[0])—VCRB Bits 4–5
The Data Mode bit (HD[0]) defines whether hard decision data bits are available for
performing channel equalization. In the current revision of the DSP56305, only hard
decision data bits are available.
HD[1:0]
0
1
13.5.4.5
Window Error Detection Enable (WEDE)—VCRB Bit 6
The Window Error Detection Enable (WEDE) bit, when set, enables the WED function
while performing channel decoding
13.5.4.6
Data-In Interrupt Enable (DIIE)—VCRB Bit 8
The Data-In Interrupt Enable (DIIE) bit, when set, enables the interrupts caused by
request for data input (DREQ bit in VSTR).
13.5.4.7
Buffer Full Interrupt Enable (BFIE)—VCRB Bit 10
The Data Buffer Full Interrupt Enable (BFIE) bit, when set, enables the interrupts caused
by output-buffer full signal (DOBF bit in VSTR is set).
13.5.4.8
Data Out Interrupt Enable (DOIE)—VCRB Bit 11
The Data Out Interrupt Enable (DOIE) bit, when set, enables the interrupts caused by
data ready in the output buffer (DRDY bit in VSTR is set).
13.5.4.9
Processing Done Interrupt Enable (DNIE)—VCRB Bit 12
The Processing Done Interrupt Enable (DNIE) bit, when set, enables the interrupts
caused by done processing signal (DONE bit in VSTR is set).
13.5.4.10
Operation Complete Interrupt Enable (OCIE)—VCRB Bit 13
The Operation Complete Interrupt Enable (OCIE) bit, when set, enables the interrupts
caused by operation complete signal (OPC bit in VSTR is set).
13.5.4.11
Reserved Bits—VCRB Bits 2, 5, 9, 14–15
These bits are reserved and should be written with zero.
13-22
Table 13-5 Data Modes
Data Mode
Hard Data
hard values: $7FFF00 = 1 / $80000 = 0
Reserved
DSP56305 User's Manual
VDOR Content (24-bit)
MOTOROLA
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