Fcop Enable (Fen)—Fcsr Bit 0; Figure 12-2 Fcop Control/Status Register (Fcsr); Fcop Operation Mode (Fom[1:0])—Fcsr Bits 4–5; Table 12-4 Fcop Operation Modes - Motorola DSP56305 User Manual

Filter Co-Processor
Programming Model
15 14 13 12
FDOBF FDIBE FSAT FDOIE FDIIE
Reserved unused bit, read as zero, should be written with zero for future compatibility
Reserved bit for internal use (such as testing), must be written with zero for proper operation

Figure 12-2 FCOP Control/Status Register (FCSR)

12.4.6.1 FCOP Enable (FEN)—FCSR Bit 0
The FCOP Enable (FEN) read/write control bit, when set, enables FCOP operation.
When FEN is cleared, the FCOP is disabled and is in the FCOP individual reset state. In
this state, the FCNT contents and the FCSR control bits are unchanged, while the FCSR
status bits and internal logic bits are reset to the same state produced by hardware or
software reset. The status bits are cleared (for instance FDIBE, FDOIE, FSAT). The rest of
the control bits in FCSR and other registers remain unchanged. The internal logic is
cleared, hence the data remaining in FDIR, FDOR, and FCIR become meaningless.
12.4.6.2 FCOP Operation Mode (FOM[1:0])—FCSR Bits 4–5
The FCOP Operation Mode (FOM[1:0]) read/write control bits select the operation
mode. The operation modes are shown in Table 12-4. FOM[1:0] should only be changed
when FCOP is in the FCOP individual reset state (FEN = 0), otherwise improper
operation may result. FOM[1:0] are cleared by hardware or software reset. For a detailed
description of FCOP operation in the various modes, refer to Figure 12.5.
FOM1 FOM0 Mode
0 0
0 1
1 0
1 1
12-10
11 10 9
FDCM

Table 12-4 FCOP Operation Modes

0 Real FIR Filter
1 Full Complex FIR Filter
2 Complex FIR filter with alternate Pure Real/Imaginary outputs
3 Optimized Complex Correlation
DSP56305 User's Manual
8 7 6 5
FOM1 FOM0
Mode Function
4 3 2 1
MOTOROLA
0
FEN
AA1119