Page 1 DSP56000 24-BIT DIGITAL SIGNAL PROCESSOR FAMILY MANUAL Motorola, Inc. Semiconductor Products Sector DSP Division 6501 William Cannon Drive, West Austin, Texas 78735-8598...
Page 2 Order this document by DSP56KFAMUM/AD Motorola reserves the right to make changes without further notice to any products herein to im- prove reliability, function or design. Motorola does not assume any liability arising out of the appli- cation or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Page 3 Page B-11, An inch below the middle of the page - Replace the “ cir ” instruction with “ clr ”. Page B-16, 7 instruction from bottom - Replace “ lsl A,n0 ” with “ lsl B A,n0 ”. © MOTOROLA INC., 1995...
Page 5 Motorola product could create a situation where personal injury or death may occur.
Page 6: Table Of Contents
DATA REPRESENTATION AND ROUNDING ..... . .3-10 DOUBLE PRECISION MULTIPLY MODE ......3-16 MOTOROLA TABLE OF CONTENTS...
Page 7 NORMAL PROCESSING STATE ........7-3 EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING) ..7-10 TABLE OF CONTENTS MOTOROLA...
Page 8 10.11 USING THE OnCE ......... . .10-20 MOTOROLA...
Page 9 MOTOROLA DSP NEWS ........11-16...
Page 10 4-13 Modulo Modifier Example ........4-21 MOTOROLA LIST of FIGURES Revision 2.1...
Page 11 7-12 JSR Second Instruction of a Fast Interrupt ......7-32 viii LIST of FIGURES MOTOROLA...
Page 12 LMS FIR Adaptive Filter ........B-11 Real Input FFT Based on Glenn Bergland Algorithm....B-12 MOTOROLA LIST of FIGURES...
Page 13 MOVEP Timing Summary ........A-302 LIST of TABLES MOTOROLA...
Page 14 A-31 Special Case #2 ..........A-334 27-MHz Benchmark Results for the DSP56001R27 ....B-4 MOTOROLA LIST of TABLES...
Page 15 List of Tables (Continued) Table Page Number Title Number LIST of TABLES MOTOROLA...
Page 16: Dsp56K Family Introduction
SECTION 1 DSP56K FAMILY INTRODUCTION MOTOROLA DSP56K FAMILY INTRODUCTION 1 - 1...
Page 17 SECTION CONTENTS SECTION 1.1 INTRODUCTION ................ 3 SECTION 1.2 ORIGIN OF DIGITAL SIGNAL PROCESSING ......3 SECTION 1.2 SUMMARY OF DSP56K FAMILY FEATURES ......9 SECTION 1.3 MANUAL ORGANIZATION ............11 1 - 2 DSP56K FAMILY INTRODUCTION MOTOROLA...
Page 18: Introduction
DSP56002 and the DSP56004. Note: The DSP56000 and the DSP56001 are not based on the central processing module architecture and should not be used with this manual. They will continue to be described in the DSP56000/DSP56001 User’s Manual (DSP56000UM/AD Rev.
Page 19: Origin Of Digital Signal Processing
The DSP output is processed by a D/A converter and is low-pass filtered to remove the effects of digitizing. In summary, the advantages of using the DSP include the following: 1- 4 DSP56K FAMILY INTRODUCTION MOTOROLA...
Page 20 FIR FILTER ∑ c k ( ) × – x(t) x(n) y(n) y(t) FINITE IMPULSE RESPONSE ANALOG IN ANALOG OUT IDEAL FILTER FREQUENCY ANALOG FILTER FREQUENCY DIGITAL FILTER FREQUENCY Figure 1-2 Digital Signal Processing MOTOROLA DSP56K FAMILY INTRODUCTION 1 - 5...
Page 21 These benchmarks and others are used independently or in combination to implement functions whose characteristics are controlled by the coefficients of the benchmarks being executed. Useful functions using these and other benchmarks include the following: 1- 6 DSP56K FAMILY INTRODUCTION MOTOROLA...
Page 22 Adaptive Differential Pulse Code Broadcast Communications Modulation (ADPCM) Transcoder Cellular Mobile Telephone Medium-Rate Vocoders Computer Noise Cancelation Array Processors Repeaters Work Stations Integrated Services Digital Network Personal Computers (ISDN) Transceivers Graphics Accelerators Secure Telephones MOTOROLA DSP56K FAMILY INTRODUCTION 1 - 7...
Page 23 Input/Output to move data in and out of the DSP MAC is the basic operation used in DSP. The DSP56K family of processors has a dual Harvard architecture optimized for MAC operations. Figure 1-3 shows how the DSP56K 1- 8 DSP56K FAMILY INTRODUCTION MOTOROLA...
Page 24: Summary Of Dsp56K Family Features
Speed — Speeds high enough to easily address applications traditionally served by low-end floating point DSPs. FIR FILTER ∑ × – x(t) x(n) y(n) y(t) MEMORY MEMORY PROGRAM ∑ ∑ Figure 1-3 DSP Hardware Origins MOTOROLA DSP56K FAMILY INTRODUCTION 1 - 9...
Page 25 • Sophisticated Debugging — Motorola’s on-chip emulation technology (OnCE) allows simple, inexpensive, and speed independent access to the internal registers for debugging. OnCE tells application programmers exactly what the status is within the registers, memory locations, buses, and even the last five instructions that were executed.
Page 26: Manual Organization
DSP56001, and also have added flexibility, speed, and functionality. • Low Power — As a CMOS part, the DSP56000/DSP56001 is inherently very low power and the STOP and WAIT instructions further reduce power requirements. MANUAL ORGANIZATION This manual describes the central processing module of the DSP56K family in detail and provides practical information to help the user: •...
Page 27 Appendix A – Instruction Set Details A detailed description of each DSP56K family instruction, its use, and its affect on the processor are presented. Appendix B – Benchmarks DSP5K family benchmark results are listed in this appendix. 1- 12 DSP56K FAMILY INTRODUCTION MOTOROLA...
Page 28: Dsp56K Central Architecture Overview
SECTION 2 DSP56K CENTRAL ARCHITECTURE OVERVIEW MOTOROLA DSP56K CENTRAL ARCHITECTURE OVERVIEW 2 - 1...
Page 29 SECTION 2.5 ADDRESS GENERATION UNIT ..........5 SECTION 2.6 PROGRAM CONTROL UNIT .............5 SECTION 2.7 MEMORY EXPANSION PORT (PORT A) ........6 SECTION 2.8 ON-CHIP EMULATOR (OnCE) ..........6 SECTION 2.9 PHASE-LOCKED LOOP (PLL) BASED CLOCKING ....6 2 - 2 DSP56K CENTRAL ARCHITECTURE OVERVIEW MOTOROLA...
Page 30: Data Buses
The bus structure supports general register-to-register, register-to-memory, and memory- to-register data movement. It can transfer up to two 24-bit words and one 56-bit word in the same instruction cycle. Transfers between buses occur in the internal bus switch. MOTOROLA DSP56K CENTRAL ARCHITECTURE OVERVIEW 2 - 3...
Page 31: Address Buses
Addresses are specified for internal X data memory and Y data memory on two unidirec- tional 16-bit buses — X address bus (XAB) and Y address bus (YAB). Program memory addresses are specified on the bidirectional program address bus (PAB). External mem- 2- 4 DSP56K CENTRAL ARCHITECTURE OVERVIEW MOTOROLA...
Page 32: Data Alu
DO loop control, and interrupt (or exception) processing. It consists of three components: the program address generator, the program decode controller, and the program interrupt controller. It contains a 15-level by 32-bit system stack memory and the following six di- MOTOROLA DSP56K CENTRAL ARCHITECTURE OVERVIEW 2 - 5...
Page 33: Memory Expansion Port (Port A)
The PLL allows the DSP to use almost any available external system clock for full-speed operation, while also supplying an output clock synchronized to a synthesized internal clock. The PLL performs frequency multiplication, skew elimination, and low-power division. 2- 6 DSP56K CENTRAL ARCHITECTURE OVERVIEW MOTOROLA...
Page 34: Data Arithmetic Logic Unit
SECTION 3 DATA ARITHMETIC LOGIC UNIT MOTOROLA DATA ARITHMETIC LOGIC UNIT 3 - 1...
Page 35 3.2.5.2 Scaling ..................10 SECTION 3.3 DATA REPRESENTATION AND ROUNDING ......10 SECTION 3.4 DOUBLE PRECISION MULTIPLY MODE ......... 16 SECTION 3.5 DATA ALU PROGRAMMING MODEL ........19 SECTION 3.6 DATA ALU SUMMARY .............. 19 3 - 2 DATA ARITHMETIC LOGIC UNIT MOTOROLA...
Page 36: Section 3.1 Data Arithmetic Logic Unit
Four 24-bit input registers • A parallel, single-cycle, nonpipelined multiply-accumulator/logic unit (MAC) • Two 48-bit accumulator registers • Two 8-bit accumulator extension registers • An accumulator shifter • Two data bus shifter/limiter circuits MOTOROLA DATA ARITHMETIC LOGIC UNIT 3 - 3...
Page 37: Overview And Data Alu Architecture
MODC/NMI 16 BITS MODB/IRQB 24 BITS MODA/IRQA RESET Figure 3-1 DSP56K Block Diagram The following paragraphs describe each of these components and provide a description of data representation, rounding, and saturation arithmetic. 3 - 4 DATA ARITHMETIC LOGIC UNIT MOTOROLA...
Page 38: Data Alu Input Registers (X1, X0, Y1, Y0)
X DATA BUS Y DATA BUS MULTIPLIER ACCUMULATOR, ROUNDING, AND LOGIC UNIT SHIFTER A (56) B (56) SHIFTER/LIMITER Figure 3-2 Data ALU MOTOROLA DATA ARITHMETIC LOGIC UNIT 3 - 5...
Page 39: Mac And Logic Unit
The logic unit performs the logical operations AND, OR, EOR, and NOT on Data ALU reg- isters. It is 24 bits wide and operates on data in the MSP portion of the accumulator. The LSP and EXT portions of the accumulator are not affected. 3 - 6 DATA ARITHMETIC LOGIC UNIT MOTOROLA...
Page 40: Data Alu A And B Accumulators
(EXT) is stored in A2 or B2 and is used when more than 48-bit accuracy is needed; the 24-bit most significant product (MSP) is stored in A1 or B1; the 24-bit least MOTOROLA DATA ARITHMETIC LOGIC UNIT 3 - 7...
Page 41: Data Alu Accumulator Registers
XDB or YDB. When individual registers A0, A1, A2, B0, B1, or B2 are specified as the source for a parallel data move, 3 - 8 DATA ARITHMETIC LOGIC UNIT MOTOROLA...
Page 42: Accumulator Shifter
Data ALU. When limiting does occur, a flag is set and latched in the status register.Two limiters allow two-word operands to be limited independently in the same instruction cycle. The two data limiters can also be com- MOTOROLA DATA ARITHMETIC LOGIC UNIT 3 - 9...
Page 43: Data Representation And Rounding
Fourier transforms to be implemented in a regular fashion. DATA REPRESENTATION AND ROUNDING The DSP56K uses a fractional data representation for all Data ALU operations. Figure 3- 3 - 10 DATA ARITHMETIC LOGIC UNIT MOTOROLA...
Page 44: Integer-To-Fractional Data Conversion
For words and long words, the most negative number that can be represented is -1 whose internal representation is $800000 and $800000000000, respectively. The most positive word is $7FFFFF or 1 - 2 and the most positive long word is $7FFFFFFFFFFF MOTOROLA DATA ARITHMETIC LOGIC UNIT 3 - 11...
Page 45: Bit Weighting And Alignment Of Operands
Y1:Y0 = Y A1:A0 = A10 B1:B0 = B10 –24 –47 –2 A2, B2 A1, B1 A0, B0 ACCUMULATOR A OR B SIGN EXTENSION OPERAND ZERO Figure 3-7 Bit Weighting and Alignment of Operands 3 - 12 DATA ARITHMETIC LOGIC UNIT MOTOROLA...
Page 46: Integer/Fractional Number Comparison
(the A1 or B1 register is rounded according to the contents of the A0 or B0 register). The rounding method is called round-to-nearest (even) number, or convergent rounding. The usual rounding method rounds up any value above one-half MOTOROLA DATA ARITHMETIC LOGIC UNIT 3 - 13...
Page 47: Integer/Fractional Multiplication Comparison
A1 (or B1) register. If scaling is set in the status register, the resulting number will be rounded as it is put on the data bus. How- ever, the contents of the register are not scaled. 3 - 14 DATA ARITHMETIC LOGIC UNIT MOTOROLA...
Page 48: Convergent Rounding
XX . . XX XXX . . . XXX0110 000 ..000 48 47 24 23 48 47 24 23 *A0 is always clear; performed during RND, MPYR, MACR Figure 3-10 Convergent Rounding MOTOROLA DATA ARITHMETIC LOGIC UNIT 3 - 15...
Page 49: Double Precision Multiply Mode
;LSP*LSP x1,y0,a a0,y:(r0) ;shifted(a)+ ; MSP*LSP x0,y1,a ;a+LSP*MSP y1,x1,a a0,x:(r0)+ ;shifted(a)+ ; MSP*MSP move a,l:(r0)+ andi #$bf,mr ;exit mode non-Data ALU operation ;pipeline delay Figure 3-11 Full Double Precision Multiply Algorithm 3 - 16 DATA ARITHMETIC LOGIC UNIT MOTOROLA...
Page 50 DM bit is cleared and the least significant part of the result is saved to memory. The most significant parts of the double precision values are then multiplied by the single pre- MOTOROLA DATA ARITHMETIC LOGIC UNIT 3 - 17...
Page 51 ;exit DP mode move a0,x:(r0)+ ;save DP1 move a1,y0 move a2,a move y0,a0 ;a2:a1 a1:a0 x0,y1,a x:(r1)+,x0 y:(r5)+,y1 ;load MSPi and SPi move a,l:(r0)+ ;save DP3_DP2 × Figure 3-13 Single Double Multiply-Accumulate Algorithm 3 - 18 DATA ARITHMETIC LOGIC UNIT MOTOROLA...
Page 52: Data Alu Programming Model
The final result is then stored in one of the accumulators as a valid 56-bit number. The condition code bits are set based on the rounded output of the logic unit. MOTOROLA DATA ARITHMETIC LOGIC UNIT 3 - 19...
Page 53: Data Alu Summary
DATA ALU SUMMARY 3 - 20 DATA ARITHMETIC LOGIC UNIT MOTOROLA...
Page 54: Address Generation Unit
SECTION 4 ADDRESS GENERATION UNIT MOTOROLA ADDRESS GENERATION UNIT 4 - 1...
Page 55 4.4.1.7 Predecrement By 1 ..............13 4.4.2 Address Modifier Arithmetic Types .............14 4.4.2.1 Linear Modifier (Mn=$FFFF) ............16 4.4.2.2 Modulo Modifier ................18 4.4.2.3 Reverse-Carry Modifier (Mn=$0000) .......... 22 4.4.2.4 Address-Modifier-Type Encoding Summary ....... 25 4 - 2 ADDRESS GENERATION UNIT MOTOROLA...
Page 56: Address Generation Unit And Addressing Modes
Each register can also be written by the output of its respective ad- dress ALU. One Rn register from the low address ALU and one Rn register from the high address ALU can be accessed in a single instruction. MOTOROLA ADDRESS GENERATION UNIT 4 - 3...
Page 57: Offset Register Files (Nn)
N0 - N3 and N4 - N7, which contain either data or offset values used to update address pointers. Each offset register can be read or written by the 4 - 4 ADDRESS GENERATION UNIT MOTOROLA...
Page 58: Modifier Register Files (Mn)
(called an offset adder), which can add 1) plus one, 2) minus one, 3) the contents of the respective offset register N, or 4) the twos complement of N to the contents of the MOTOROLA ADDRESS GENERATION UNIT 4 - 5...
Page 59: Programming Model
Automatic up- dating is available when using address register indirect addressing. The Mn registers can be programmed for linear addressing, modulo addressing, and bit-reverse addressing. 4 - 6 ADDRESS GENERATION UNIT MOTOROLA...
Page 60: Address Register Files (R0 - R3 And R4 - R7)
Each address register, Rn, has its own offset register, Nn, associated with it. MOTOROLA ADDRESS GENERATION UNIT 4 - 7...
Page 61: Addressing
Since the register direct and special addressing modes do not nec- essarily use the AGU registers, they are described in SECTION 6 - INSTRUCTION SET INTRODUCTION. The address register indirect addressing modes use the registers in 4 - 8 ADDRESS GENERATION UNIT MOTOROLA...
Page 62: Address Register Indirect Modes
The address of the operand is in the address register, Rn (see Table 4-1 and Figure 4-6). After the operand address is used, it is decremented by 1 and stored in the same address register. This mode can be used for making XY: memory references and for MOTOROLA ADDRESS GENERATION UNIT 4 - 9...
Page 63: Postincrement By Offset Nn
After the operand address is used, it is incremented by the contents of the Nn register and stored in the same address register. The contents of the Nn register are unchanged. This mode can be used for making XY: memory references and for modifying the contents of 4 - 10 ADDRESS GENERATION UNIT MOTOROLA...
Page 64: Postdecrement By Offset Nn
After the operand address is used, it is decremented by the contents of the Nn register and stored in the same address register. The contents of the Nn register are unchanged. This mode cannot be used for making XY: memory references, but it can be used to mod- MOTOROLA ADDRESS GENERATION UNIT 4 - 11...
Page 65: Indexed By Offset Nn
The address of the operand is the sum of the contents of the address register, Rn, and the contents of the address offset register, Nn (see Table 4-1 and Figure 4-9). The con- tents of the Rn and Nn registers are unchanged. This addressing mode, which requires 4 - 12 ADDRESS GENERATION UNIT MOTOROLA...
Page 66: Predecrement By 1
Rn are decremented and stored in the same address register. This addressing mode re- quires an extra instruction cycle. This mode cannot be used for making XY: memory references, nor can it be used for modifying the contents of Rn without an associated data MOTOROLA ADDRESS GENERATION UNIT 4 - 13...
Page 67: Address Modifier Arithmetic Types
The address ALU supports linear, modulo, and reverse-carry arithmetic for all address register indirect modes. These arithmetic types easily allow the creation of data structures in memory for FIFOs (queues), delay lines, circular buffers, stacks, and bit-reversed FFT buffers. 4 - 14 ADDRESS GENERATION UNIT MOTOROLA...
Page 68: Address Register Indirect — Indexed By Offset Nn
For modulo arithmetic, the contents of Mn also specifies the modulus, or the size of the memory buffer whose addresses will be refer- enced. See Table 4-2 for a summary of the address modifiers implemented on the MOTOROLA ADDRESS GENERATION UNIT 4 - 15...
Page 69: Linear Modifier (Mn=$Ffff)
The range of values can be considered as signed (Nn from –32,768 to + 32,767) or unsigned (Nn from 0 to + 65,535) since there is no arithmetic 4 - 16 ADDRESS GENERATION UNIT MOTOROLA...
Page 70: Modulo Modifier
(base address plus M–1), it will wrap around through the base address (lower boundary). Alternatively, assuming the (Rn)- indirect addressing mode, if the address decrements past the lower boundary MOTOROLA ADDRESS GENERATION UNIT 4 - 17...
Page 71: Address Modifier Summary
Multiple Wrap-Around Modulo 2 Reserved 87FF Multiple Wrap-Around Modulo 2 Reserved 8FFF Multiple Wrap-Around Modulo 2 Reserved 9FFF Multiple Wrap-Around Modulo 2 Reserved BFFF Multiple Wrap-Around Modulo 2 Reserved FFFF Linear (Modulo 2 4 - 18 ADDRESS GENERATION UNIT MOTOROLA...
Page 72: Circular Buffer
15 locations. The lower boundary = L x (2 ) where 2 21; therefore, k=5 and the lower address boundary must be a multiple of 32. The lower boundary may be chosen MOTOROLA ADDRESS GENERATION UNIT 4 - 19...
Page 73: Linear Addressing With A Modulo Modifier
MOVE B0,X:(R0)+ N0 instruction (where R0=6, M0=5, and N0=0) would ap- parently leave R0 unchanged since N0=0. However, since R0 is above the upper boundary, the AGU calculates R0+ N0–M0–1 for the new contents of R0 and sets R0=0. 4 - 20 ADDRESS GENERATION UNIT MOTOROLA...
Page 74: Modulo Modifier Example
LSBs, where 2 = M, and therefore must be a multiple of 2 . The upper boundary is the lower boundary plus the modulo size minus one (base address plus M-1). MOTOROLA ADDRESS GENERATION UNIT 4 - 21...
Page 75: Reverse-Carry Modifier (Mn=$0000)
FFTs up to 65,536 points. To make bit-reverse addressing work correctly for a 2 point FFT, the following proce- dures must be used: 1. Set Mn=0; this selects reverse-carry arithmetic. (k–1) 2. Set Nn=2 4 - 22 ADDRESS GENERATION UNIT MOTOROLA...
Page 76: Bit-Reverse Addressing Sequence Example
The reverse-carry modifier only works when the base address of the FFT data buffer is a multiple of 2 , such as 1,024, 2,048, 3,072, etc. The use of addressing modes other than postincrement by + Nn is possible but may not provide a useful result. MOTOROLA ADDRESS GENERATION UNIT 4 - 23...
Page 77: Bit-Reverse Address Calculation Example
Bits 1 and 8 are swapped. • Bits 2 and 7 are swapped. • Bits 3 and 6 are swapped. • Bits 4 and 5 are swapped. The result is Rn equals 3,584. 4 - 24 ADDRESS GENERATION UNIT MOTOROLA...
Page 78: Address-Modifier-Type Encoding Summary
This boundary creates a circular buffer so that, if the address register is pointing within the boundaries, addressing past a boundary causes a circular wraparound to the other boundary. MOTOROLA ADDRESS GENERATION UNIT 4 - 25...
Page 79: Address Modifier Summary
POSTINCREMENT BY OFFSET N0: R0 = 72 = 0100 1000 POSTINCREMENT BY OFFSET N0: R0 = 68 = 0100 0100 POSTINCREMENT BY OFFSET N0: R0 = 76 = 0100 1100 Figure 4-15 Address Modifier Summary 4 - 26 ADDRESS GENERATION UNIT MOTOROLA...
Page 80: Program Control Unit
SECTION 5 PROGRAM CONTROL UNIT MOTOROLA PROGRAM CONTROL UNIT 5 - 1...
Page 81 5.4.5.2 Stack Error Flag (Bit 4) ..............16 5.4.5.3 Underflow Flag (Bit 5) ..............16 5.4.5.4 Reserved Stack Pointer Registration (Bits 6–23) ......17 5.4.6 Loop Address Register ............... 17 5.4.7 Loop Counter Register ............... 17 5.4.8 Programming Model Summary ............17 5 - 2 PROGRAM CONTROL UNIT MOTOROLA...
Page 82: Section 5.1 Program Control Unit
Each location in the SS is addressable as a 16-bit register, system stack high (SSH) and system stack low (SSL). The stack pointer (SP) points to the SS locations. CLOCK INTERRUPTS 32 x 15 STACK CONTROL GLOBAL DATA BUS Figure 5-1 Program Address Generator MOTOROLA PROGRAM CONTROL UNIT 5 - 3...
Page 83: Overview
(LSBs) are significant, and the most significant bits (MSBs) are zeroed as appropriate. When they are written, only the appropriate LSBs are significant, and the MSBs are written as don’t care. 5 - 4 PROGRAM CONTROL UNIT MOTOROLA...
Page 84: Program Control Unit (Pcu) Architecture
The repeat (REP) instruction loads the LC with the number of times the next instruction is to be repeated. The instruction to be repeated is only fetched once, so throughput is in- creased by reducing external bus contention. However, REP instructions are not MOTOROLA PROGRAM CONTROL UNIT 5 - 5...
Page 85: Program Interrupt Controller
(pointed to by R4) into Y1 and postincrement R4. The second instruction, I2, should be interpreted as follows: clear accumulator A, move the contents in X0 into the location in X data memory pointed to by R0 and postincrement R0. Before the clear oper- 5 - 6 PROGRAM CONTROL UNIT MOTOROLA...
Page 86: Three-Stage Pipeline
$000005 $000005 $000005 $000005 $0006 $000006 $000006 $000005 $000005 $0007 $000007 $000007 $000007 $000007 DATA Y MEMORY AT ADDRESS $0008 $000008 $000008 $000008 $000008 $000009 $0009 $000009 $0000A2 $0000A2 Figure 5-3 Three-Stage Pipeline MOTOROLA PROGRAM CONTROL UNIT 5 - 7...
Page 87: Programming Model
This 16-bit register contains the address of the next location to be fetched from program memory space. The PC can point to instructions, data operands, or addresses of oper- ands. References to this register are always inherent and are implied by most instructions. 5 - 8 PROGRAM CONTROL UNIT MOTOROLA...
Page 88: Status Register
(ORI) and AND immediate to control register (ANDI). During processor reset, the interrupt mask bits of the MR will be set. The scaling mode bits, loop flag, and trace bit will be cleared. MOTOROLA PROGRAM CONTROL UNIT 5 - 9...
Page 89: Carry (Bit 0)
Scaling Mode U Bit Computation ⊕ No Scaling U = (Bit 47 Bit 46) ⊕ Scale Down U = (Bit 48 Bit 47) ⊕ Scale Up U = (Bit 46 Bit 45) 5 - 10 PROGRAM CONTROL UNIT MOTOROLA...
Page 90: Extension (Bit 5)
FFT operation. Typically, the bit is tested after each pass of a radix 2 FFT and, if it is set, the scaling mode should be activated in the next pass. The Block Floating Point FFT al- gorithm is described in the Motorola application note APR4/D, “Implementation of Fast Fourier Transforms on Motorola’s DSP56000/DSP56001 and DSP96002 Digital Signal Processors.”...
Page 91: Interrupt Masks (Bits 8 And 9)
Scaling Mode (Bits 10 and 11) The scaling mode bits, S1 and S0, specify the scaling to be performed in the data ALU shifter/limiter, and also specify the rounding position in the data ALU multiply-accumula- 5 - 12 PROGRAM CONTROL UNIT MOTOROLA...
Page 92: Reserved Status (Bit 12)
DSP56K family, use the OnCE trace mode described in Section 10.5.) For the DSP56000/56001, if the T bit is set at the beginning of any instruction exe- cution, a trace exception will be generated after the instruction execution is completed. If the T bit is cleared, tracing is disabled and instruction execution proceeds normally.
Page 93: Loop Flag (Bit 15)
OMR bit definitions, see the individual chip’s user manual for details on its respective op- erating modes. 5.4.4 System Stack The SS is a separate 15X32-bit internal memory divided into two banks, the SSH and the 5 - 14 PROGRAM CONTROL UNIT MOTOROLA...
Page 94: Stack Pointer Register
(selects) a 15-location stack with its four LSBs. The possible SP values are shown in Figure 5-8 and described in the following paragraphs. 5.4.5.1 Stack Pointer (Bits 0–3) The SP points to the last location used on the SS. Immediately after hardware reset, MOTOROLA PROGRAM CONTROL UNIT 5 - 15...
Page 95: Stack Error Flag (Bit 4)
STACK UNDERFLOW CONDITION STACK EMPTY (RESET); PULL CAUSES UNDERFLOW STACK LOCATION 1 STACK LOCATION 14 STACK LOCATION 15; PUSH CAUSES OVERFLOW STACK OVERFLOW CONDITION STACK OVERFLOW CONDITION AFTER DOUBLE PUSH Figure 5-8 SP Register Values 5 - 16 PROGRAM CONTROL UNIT MOTOROLA...
Page 96: Underflow Flag (Bit 5)
REP instruction 5.4.8 Programming Model Summary The complete programming model for the DSP56K central processing module is shown in Figure 5-9. Programming models for the peripherals are shown in the appropriate user manuals. MOTOROLA PROGRAM CONTROL UNIT 5 - 17...
Page 97: Dsp56K Central Processing Module Programming Model
STACK POINTER (SP) READ AS ZERO, SHOULD BE WRITTEN WITH ZERO FOR FUTURE COMPATIBILITY # READ AS SIGN EXTENSION BITS, WRITTEN AS DON’T CARE SYSTEM STACK Figure 5-9 DSP56K Central Processing Module Programming Model 5 - 18 PROGRAM CONTROL UNIT MOTOROLA...
Page 98: Instruction Set Introduction
SECTION 6 INSTRUCTION SET INTRODUCTION Fetch . . . Decode D3e D4 . . . Execute E3e E4 . . . Instruction Cycle: . . . MOTOROLA INSTRUCTION SET INTRODUCTION 6 - 1...
Page 99 SECTION 6.4 INSTRUCTION GROUPS ............20 6.4.1 Arithmetic Instructions ................ 22 6.4.2 Logical Instructions ................23 6.4.3 Bit Manipulation Instructions ............... 24 6.4.4 Loop Instructions ................24 6.4.5 Move Instructions ................26 6.4.6 Program Control Instructions .............. 27 6 - 2 INSTRUCTION SET INTRODUCTION MOTOROLA...
Page 100: Syntax
APPENDIX A - INSTRUCTION SET DETAILS. INSTRUCTION FORMATS The DSP56K instructions consist of one or two 24-bit words – an operation word and an optional effective address extension word. The general format of the operation word is MOTOROLA INSTRUCTION SET INTRODUCTION 6 - 3...
Page 101: Instruction Formats
STACK POINTER (SP) READ AS ZERO, SHOULD BE WRITTEN WITH ZERO FOR FUTURE COMPATIBILITY # READ AS SIGN EXTENSION BITS, WRITTEN AS DON’T CARE SYSTEM STACK Figure 6-1 DSP56K Central Processing Module Programming Model 6 - 4 INSTRUCTION SET INTRODUCTION MOTOROLA...
Page 102: Operand Sizes
Figure 6-3). The operand size for each instruction is either explicitly encoded in the instruction or implicitly defined by the instruction operation. Implicit instructions support some subset of the five sizes shown in Figure 6-3. MOTOROLA INSTRUCTION SET INTRODUCTION 6 - 5...
Page 103: Data Organization In Registers
Accumulator operands occupy an entire group of three registers (i.e., A2:A1:A0 or B2:B1:B0). The LSB is the right-most bit (bit 0), and the MSB is the left-most bit (bit 55). 6 - 6 INSTRUCTION SET INTRODUCTION MOTOROLA...
Page 104: Agu Registers
The notation “Rn” desig- nates one of the eight address registers, R0–R7; the notation “Nn” designates one of the eight address offset registers, N0–N7; and the notation “Mn” designates one of the eight MOTOROLA INSTRUCTION SET INTRODUCTION 6 - 7...
Page 105: Program Control Registers
DSP56K family member. In general, undefined bits are written as “don’t care” and read as zero. The 16-bit SR has the system mode register (MR) occupying the high-order eight bits and 6 - 8 INSTRUCTION SET INTRODUCTION MOTOROLA...
Page 106: Data Organization In Memory
Accumulators A and B (A1:B1, 48 Bits) *Data Move Operations: when speciﬁed as a source operand, shifting and limiting are performed. When speciﬁed as a destination operand, sign extension and zero ﬁlling are performed. MOTOROLA INSTRUCTION SET INTRODUCTION 6 - 9...
Page 107 Program Memory Reference Miscellaneous Immediate Short Data (8 Bits) #xxx Immediate Short Data (12 Bits) #xxxxxx Immediate Data (24 Bits) Immediate Short Data (5 Bits) S,Sn Source Operand Register D,Dn Destination Operand Register 6 - 10 INSTRUCTION SET INTRODUCTION MOTOROLA...
Page 108: Operand References
Data can be read or written from any address in either memory space. MOTOROLA INSTRUCTION SET INTRODUCTION 6 - 11...
Page 109 INSTRUCTION FORMATS 6.3.4.4.1 X Memory References The operand, which is in X memory space, is a word reference. Data can be transferred from memory to a register or from a register to memory. 6 - 12 INSTRUCTION SET INTRODUCTION MOTOROLA...
Page 110: Y Memory References
All indirect memory references require one address modifier, and the XY memory reference requires two address modifiers. The definition of certain instructions implies the use of specific reg- isters and addressing modes. MOTOROLA INSTRUCTION SET INTRODUCTION 6 - 13...
Page 111: Register Direct Modes
MOVE instruction, the new contents will not be available for use as a pointer until the second following instruction. 6.3.5.2 Address Register Indirect Modes The address register indirect mode description is presented in SECTION 4 - ADDRESS GENERATION UNIT. 6 - 14 INSTRUCTION SET INTRODUCTION MOTOROLA...
Page 112: Special Addressing Modes
6-9 shows the use of immediate short addressing in four examples. 6.3.5.3.4 Short Jump Address The operand occupies 12 bits in the instruction operation word, which allows addresses $0000–$0FFF to be accessed (see Figure 6-10). The address is zero extended to 16 bits MOTOROLA INSTRUCTION SET INTRODUCTION 6 - 15...
Page 113: Special Addressing – Immediate Data
Additional Instruction Execution Time (Clocks): 2 Additional Effective Address Words: 1 Figure 6-7 Special Addressing – Immediate Data when used to address program memory. This addressing mode is classified as a program reference. 6 - 16 INSTRUCTION SET INTRODUCTION MOTOROLA...
Page 114: Absolute Short
(JMP) implicitly references the PC; whereas, the repeat next instruction (REP) implicitly references LC. The registers implied and their uses are defined by the individual instruction descriptions (see APPENDIX A - INSTRUCTION SET DETAILS). 6.3.5.4 Addressing Modes Summary MOTOROLA INSTRUCTION SET INTRODUCTION 6 - 17...
Page 115 24 23 X X X X X X X X X X X X 1 F 0 0 0 0 0 0 0 0 0 0 0 23 0 23 0 23 0 23 6 - 18 INSTRUCTION SET INTRODUCTION MOTOROLA...
Page 116: Instruction Groups
Each instruction group is described in the following paragraphs; detailed information on each instruction is given in APPENDIX A - INSTRUCTION SET DETAILS. 6.4.1 Arithmetic Instructions The arithmetic instructions, which perform all of the arithmetic operations within the data MOTOROLA INSTRUCTION SET INTRODUCTION 6 - 19...
Page 117: Special Addressing – Absolute Short Address
3 4 F 5 E 6 $0000 $0000 Assembler Syntax: aa Memory Spaces: P:, X:, Y:, L: Additional Instruction Execution Time (Clocks): 0 Additional Effective Address Words: 0 Figure 6-11 Special Addressing – Absolute Short Address 6 - 20 INSTRUCTION SET INTRODUCTION MOTOROLA...
Page 118: Section 6.4 Instruction Groups
GDB during a data ALU operation. This parallel movement allows new data to be prefetched for use in subsequent instructions and allows results calculated in previous instructions to be stored. The following list contains the arithmetic instructions: MOTOROLA INSTRUCTION SET INTRODUCTION 6 - 21...
Page 119 C = Program Control Unit Register Reference D = Data ALU Register Reference A = AGU Register Reference X = X Memory Reference Y = Y Memory Reference L = L Memory Reference XY = XY Memory Reference 6 - 22 INSTRUCTION SET INTRODUCTION MOTOROLA...
Page 120: Logical Instructions
A logical instruction uses only the MSP portion of the A and B registers (A1 and B1). *These instructions do not allow parallel data moves. **Certain applications of these instructions do not allow parallel data moves. MOTOROLA INSTRUCTION SET INTRODUCTION 6 - 23...
Page 121 AND Immediate to Control Register Logical Exclusive OR Logical Shift Left Logical Shift Right Logical Complement Logical Inclusive OR OR Immediate to Control Register Rotate Left Rotate Right *These instructions do not allow parallel data moves. 6 - 24 INSTRUCTION SET INTRODUCTION MOTOROLA...
Page 122: Bit Manipulation Instructions
B. The current 16-bit LA and 16-bit LC registers are pushed onto the SS to allow nested loops. C. The LC register is initiated with the loop count value specified in the DO instruction. MOTOROLA INSTRUCTION SET INTRODUCTION 6 - 25...
Page 123 DO loops can be stacked indefinitely. The ENDDO instruction is not used for normal termination of a DO loop; it is only used to terminate a DO loop before the LC has been decremented to one. 6 - 26 INSTRUCTION SET INTRODUCTION MOTOROLA...
Page 124: Move Instructions
Example B depicts the following sequence: 1) register X0 is added to register A and the result is placed in register A; and 2) registers A and B are moved, respectively, to the loca- MOTOROLA INSTRUCTION SET INTRODUCTION 6 - 27...
Page 125: Program Control Instructions
Optional data transfers over the XDB and YDB may be specified in some of the program control instructions. The following list contains the program control instructions: DEBUG Enter Debug Mode DEBUGcc Enter Debug Mode Conditionally Illegal Instruction Jump Conditionally Jump 6 - 28 INSTRUCTION SET INTRODUCTION MOTOROLA...
Page 126 B2 SIGN EXTENDED B0 CLEARED Y MEMORY X MEMORY Example B ADD X0,A AB,L:(R2)+N2 LONG MEMORY MOVE + N2 X MEMORY Y MEMORY A,B ARE SHIFTED AND LIMITED Figure 6-16 Parallel Move Examples MOTOROLA INSTRUCTION SET INTRODUCTION 6 - 29...
Page 127 INSTRUCTION GROUPS 6 - 30 INSTRUCTION SET INTRODUCTION MOTOROLA...
Page 128: Processing States
SECTION 7 PROCESSING STATES STOP NORMAL WAIT RESET EXCEPTION MOTOROLA PROCESSING STATES 7 - 1...
Page 129 7.3.6 Instructions Preceding the Interrupt Instruction Fetch ......25 7.3.7 Interrupt Instruction Execution ............26 SECTION 7.4 RESET PROCESSING STATE ..........33 SECTION 7.5 WAIT PROCESSING STATE ............. 36 SECTION 7.6 STOP PROCESSING STATE ............ 37 7 - 2 PROCESSING STATES MOTOROLA...
Page 130: Section 7.1 Processing States
Table 7-1 Instruction Pipelining Instruction Cycle Operation • • • Fetch • • • Decode • • • Execute • • • MOTOROLA PROCESSING STATES 7 - 3...
Page 131: Normal Processing State
ORI’s execution time slot. The following code produces the expected results of reading the internal ROM: ORI #04,OMR ;Sets DE bit at execution time slot ;Delays the MOVE so it will read the updated memory map MOVE x:$100,a ;Reads internal ROM 7 - 4 PROCESSING STATES MOTOROLA...
Page 132 OMR before the JMP instruction formed the fetch address. As a result, the jump would fetch the instruction at P:$0000 of the bootstrap ROM (MOVE #$FFE9,R2). The OMR would then change due to the MOVEC instruction, and the next instruction would be the MOTOROLA PROCESSING STATES 7 - 5...
Page 133 II+1 INST 3 (See Note 1) INST 2 INST 2 II+1 INST 3 INST 3 INST 3 II+1 INST 4 INST 4 INST 4 INST 4 • • • • • • • • 7 - 6 PROCESSING STATES MOTOROLA...
Page 134 • • 2. Program flow with interrupts after interrupts are re-enabled: • • ANDI #00,MR ;Enable interrupts INST 1 ;Uninterruptable INST 2 ;Uninterruptable INST 3 ;II fetched INST 4 ;II+1 fetched II+1 • • MOTOROLA PROCESSING STATES 7 - 7...
Page 135: Summary Of Pipeline-Related Restrictions
Proper DO loop operation is guaranteed if no instruction starting at address LA-2, LA-1, or LA specifies the program controller registers SR, SP, SSL, LA, LC, or (implicitly) PC as a destination register, or specifies SSH as a source or a destination register. 7 - 8 PROCESSING STATES MOTOROLA...
Page 136 ANDI MR, ANDI CCR ORI MR, ORI CCR The RTS instruction must not be immediately preceded by any of the following instruc- tions: BCHG/BCLR/BSET SSH, SSL, or SP MOVEC/MOVEM to SSH, SSL, or SP MOVEC/MOVEM from SSH MOTOROLA PROCESSING STATES 7 - 9...
Page 137: Exception Processing State (Interrupt Processing)
Section 7.3.1.) EXCEPTION PROCESSING STATE (INTERRUPT PROCESSING) The exception processing state is associated with interrupts that can be generated by conditions inside the DSP or from external sources. In digital signal processing, one of 7 - 10 PROCESSING STATES MOTOROLA...
Page 138: Interrupt Types
Activities 2 and 3 listed above require two additional control cycles, which effectively make the interrupt pipeline five levels deep. 7.3.1 Interrupt Types The DSP56K relies on two types of interrupt routines: fast and long. The fast interrupt MOTOROLA PROCESSING STATES 7 - 11...
Page 139: Interrupt Priority Structure
(except that hardware RESET, NMI, stack error, trace, and SWI can always interrupt). 5. The trace bit in the SR is cleared (in the DSP56000/56001 only). The long interrupt routine should be terminated by an RTI. Long interrupt routines are interruptible by higher priority interrupts.
Page 140: Fast And Long Interrupt Examples
EXPLICIT RETURN $0303 MOVE FROM INTERRUPT RECOGNIZED $0304 (b) DSP56K Long Interrupt Figure 7-1 Fast and Long Interrupt Examples and their IPLs are listed in Table 7-6. For information on on-chip peripheral interrupt pri- MOTOROLA PROCESSING STATES 7 - 13...
Page 141: Interrupt Priority Levels
IRQB MODE RESERVED FOR EXPANSION RESERVED FOR PERIPHERAL IPL LEVELS Bits 6 to 9 are reserved, read as zero and should be written with zero for future compatibility. Figure 7-2 Interrupt Priority Register (Addr X:$FFFF) 7 - 14 PROCESSING STATES MOTOROLA...
Page 142: Interrupt Sources
— — — Lowest — — — Levels 0, 1, 2 (Maskable) Higher IRQA (External Interrupt) IRQA Mode Bits 0 and 1 $FFFF Lower IRQB (External Interrupt) IRQB Mode Bits 3 and 4 $FFFF MOTOROLA PROCESSING STATES 7 - 15...
Page 143: Hardware Interrupt Sources
Edge-sensitive interrupts are latched as pending on the high-to-low transition of the interrupt input and are automatically cleared when the interrupt is ser- viced. 7 - 16 PROCESSING STATES MOTOROLA...
Page 144: Interrupting An Swi
= FIRST SWI VECTOR (ONE-WORD JSR) ii4 = SECOND SWI VECTOR n = NORMAL INSTRUCTION WORD n4 = SWI sw = INSTRUCTIONS PERTAINING TO THE SWI LONG INTERRUPT ROUTINE Figure 7-3 Interrupting an SWI MOTOROLA PROCESSING STATES 7 - 17...
Page 145: Software Interrupt Sources
The illegal instruction is useful for triggering the illegal interrupt service routine to see if the III routine can recover from illegal instructions. 7 - 18 PROCESSING STATES MOTOROLA...
Page 146: Illegal Instruction Interrupt Serviced By A Fast Interrupt
— — INSTRUCTION CYCLE COUNT = INTERRUPT = INTERRUPT INSTRUCTION WORD II = ILLEGAL INSTRUCTION n = NORMAL INSTRUCTION WORD (b) Program Controller Pipeline Figure 7-4 Illegal Instruction Interrupt Serviced by a Fast Interrupt MOTOROLA PROCESSING STATES 7 - 19...
Page 147: Illegal Instruction Interrupt Serviced By A Long Interrupt
— — INSTRUCTION CYCLE COUNT = INTERRUPT = INTERRUPT INSTRUCTION WORD II = ILLEGAL INSTRUCTION n = NORMAL INSTRUCTION WORD (b) Program Controller Pipeline Figure 7-5 Illegal Instruction Interrupt Serviced by a Long Interrupt 7 - 20 PROCESSING STATES MOTOROLA...
Page 148: Repeated Illegal Instruction
LC because the LA instruction is being executed. At this point, the illegal instruction will trigger the III. The result is that the loop state machine decrements LC twice in one loop due to the presence of the illegal opcode at the LA location. MOTOROLA PROCESSING STATES 7 - 21...
Page 149: Other Interrupt Sources
This trace mode generates a trace exception after each instruc- tion executed (see Figure 7-7), which can be used by a debugger program to monitor the execution of a program. (With members of the DSP56K family other than DSP56000/ 56001, use the OnCE trace mode described in 10.5.) The trace bit in the SR defines the trace mode.
Page 150: Trace Exception
DECODE TRACE PROGRAM NOP NOP EXECUTE TRACE PROGRAM INSTRUCTION CYCLE COUNT = INTERRUPT = INTERRUPT INSTRUCTION WORD II = ILLEGAL INSTRUCTION n = NORMAL INSTRUCTION WORD (b) Program Controller Pipeline Figure 7-7 Trace Exception MOTOROLA PROCESSING STATES 7 - 23...
Page 151: Interrupt Arbitration
(i.e., JMP, JSR, etc.) that would normally ignore the instructions in the pipe. After the interrupt instruction fetch, the PC will point to the instruction that would have been fetched if the interrupt instructions had not been inserted. 7 - 24 PROCESSING STATES MOTOROLA...
Page 152: Instructions Preceding The Interrupt Instruction Fetch
4. The REP instruction and the instruction being repeated are not interruptible. 5. If the trace bit in the SR (DSP56000/56001 only) is set, the only interrupts that will be processed are the hardware RESET, III,NMI, stack error, and trace.
Page 153: Interrupt Instruction Execution
4. The fast interrupt routine may contain any single two-word instruction or any two one-word instructions except SWI, STOP, and WAIT. 5. The PC, which contains the address of the next instruction to be executed in normal processing remains unchanged during a fast interrupt routine. 7 - 26 PROCESSING STATES MOTOROLA...
Page 154: Fast Interrupt Service Routine
INTERRUPT CONTROL CYCLE 1 INTERRUPT CONTROL CYCLE 2 FETCH DECODE EXECUTE INSTRUCTION CYCLE COUNT = INTERRUPT = INTERRUPT INSTRUCTION WORD n = NORMAL INSTRUCTION WORD (b) Program Controller Pipeline Figure 7-8 Fast Interrupt Service Routine MOTOROLA PROCESSING STATES 7 - 27...
Page 155: Two Consecutive Fast Interrupts
INTERRUPT CONTROL CYCLE 1 INTERRUPT CONTROL CYCLE 2 FETCH DECODE EXECUTE INSTRUCTION CYCLE COUNT = INTERRUPT = INTERRUPT INSTRUCTION WORD n = NORMAL INSTRUCTION WORD (b) Program Controller Pipeline Figure 7-9 Two Consecutive Fast Interrupts 7 - 28 PROCESSING STATES MOTOROLA...
Page 156 A REP instruction and the instruction that follows it are treated as a single two-word instruction, regardless of how many times it repeats the second instruction of the pair. Instruction fetches are suspended and will be reactivated only after the LC is decre- MOTOROLA PROCESSING STATES 7 - 29...
Page 157: Long Interrupt Service Routine
INTERRUPT CONTROL CYCLE 1 INTERRUPT CONTROL CYCLE 2 FETCH — DECODE EXECUTE INSTRUCTION CYCLE COUNT = INTERRUPT = INTERRUPT INSTRUCTION WORD n = NORMAL INSTRUCTION WORD (b) Program Controller Pipeline Figure 7-10 Long Interrupt Service Routine 7 - 30 PROCESSING STATES MOTOROLA...
Page 158: Jsr First Instruction Of A Fast Interrupt
INTERRUPT CONTROL CYCLE 2 FETCH — — DECODE EXECUTE INSTRUCTION CYCLE COUNT = INTERRUPT = INTERRUPT INSTRUCTION WORD n = NORMAL INSTRUCTION WORD (b) Program Controller Pipeline Figure 7-11 JSR First Instruction of a Fast Interrupt MOTOROLA PROCESSING STATES 7 - 31...
Page 159: Jsr Second Instruction Of A Fast Interrupt
FETCH — — DECODE EXECUTE NOP n2 INSTRUCTION CYCLE COUNT = INTERRUPT = INTERRUPT INSTRUCTION WORD n = NORMAL INSTRUCTION WORD (b) Program Controller Pipeline Figure 7-12 JSR Second Instruction of a Fast Interrupt 7 - 32 PROCESSING STATES MOTOROLA...
Page 160: Reset Processing State
10. begins program execution at program memory address defined by the state of bits MODA, MODB, and MODC in the OMR. The first instruction must be fetched and then decoded before executing. Therefore, the first instruction execution is two instruction cycles after the first instruction fetch. MOTOROLA PROCESSING STATES 7 - 33...
Page 161: Interrupting An Rep Instruction
INTERRUPT CONTROL CYCLE 2 FETCH DECODE EXECUTE INSTRUCTION CYCLE COUNT = INTERRUPT = INTERRUPT INSTRUCTION WORD n = NORMAL INSTRUCTION WORD i% = INTERRUPT REJECTED (b) Program Controller Pipeline Figure 7-13 Interrupting an REP Instruction 7 - 34 PROCESSING STATES MOTOROLA...
Page 162: Interrupting Sequential Rep Instructions
EXECUTE REP NOP REP NOP n6 INSTRUCTION CYCLE COUNT = INTERRUPT = INTERRUPT INSTRUCTION WORD n = NORMAL INSTRUCTION WORD i% = INTERRUPT REJECTED (b) Program Controller Pipeline Figure 7-14 Interrupting Sequential REP Instructions MOTOROLA PROCESSING STATES 7 - 35...
Page 163: Wait Processing State
The internal clocks are not turned off, and the net effect is that of executing eight NOP instructions between the execution of n2 and ii1. 7 - 36 PROCESSING STATES MOTOROLA...
Page 164: Stop Processing State
Trace or stack errors that were pending, remain pending. The priority levels of the peripherals remain as they were before the STOP instruction was executed. The on-chip peripherals are held in their respective individual reset states while in the stop state. MOTOROLA PROCESSING STATES 7 - 37...
Page 165: Stop Instruction Sequence
RESUME STOP CYCLE COUNT 4, CLOCK STOPPED INTERRUPTS ENABLED 131,072 T OR 16 T CYCLE COUNT STARTED IRQA = INTERRUPT REQUEST A SIGNAL n = NORMAL INSTRUCTION WORD STOP = INTERRUPT INSTRUCTION WORD Figure 7-17 STOP Instruction Sequence 7 - 38 PROCESSING STATES MOTOROLA...
Page 166: Stop Instruction Sequence Followed By Irqa
At the end of the 128K T cycle delay period, the chip restarts instruction processing, completes stop cycle 4 (interrupt arbitration occurs at this time), and executes stop cycles 5, 6, 7, and 8 (it takes 17T from the end of the 128K T delay to MOTOROLA PROCESSING STATES 7 - 39...
Page 167 However, there is an additional delay if the internal oscillator is used. An indeterminate period of time is needed for the oscillator to begin oscillating and then sta- bilize its amplitude. The processor will still count 131,072 T cycles (or 16 T cycles), but 7 - 40 PROCESSING STATES MOTOROLA...
Page 168 If the user wishes to use the 128K T (or 16 T) delay counter, it can be started by asserting IRQA for a short time (about two clock cycles). MOTOROLA PROCESSING STATES 7 - 41...
Page 169: Stop Instruction Sequence Recovering With Reset
— STOP CYCLE COUNT CLOCK STOPPED = INTERRUPT IRESET = NORMAL INSTRUCTION WORD nA, nB, nC = INSTRUCTIONS IN RESET ROUTINE STOP = INTERRUPT INSTRUCTION WORD Figure 7-19 STOP Instruction Sequence Recovering with RESET 7 - 42 PROCESSING STATES MOTOROLA...
Page 170 STOP PROCESSING STATE MOTOROLA PROCESSING STATES 7 - 43...
Page 171 STOP PROCESSING STATE 7 - 44 PROCESSING STATES MOTOROLA...
Page 172 SECTION 8 PORT A MOTOROLA PORT A 8 - 1...
Page 173: Port A Interface
8.2.3 Port A Bus Control Signals ..............6 8.2.3.1 Read Enable (RD) ..............6 8.2.3.2 Write Enable (WR) ..............6 8.2.3.3 Port A Access Control Signals ............ 6 8.2.4 Interrupt and Mode Control ..............6 8.2.5 Port A Wait States ................6 8 - 2 PORT A MOTOROLA...
Page 174: Port A Overview
(using no-wait-state mem- ory which is discussed in Section 8.2.5.) Figure 8-1 shows the port A signals divided into their three functional groups: address bus MOTOROLA PORT A 8 - 3...
Page 175: Port A Interface
DS - DATA MEMORY SELECT LOGIC X/Y - X MEMORY/Y MEMORY SELECT BUS ACCESS CONTROL PINS Figure 8-1 Port A Signals signals (A0-A15), data bus signals (D0-D15), and bus control. The bus control signals can 8 - 4 PORT A MOTOROLA...
Page 176 8.2.2 Port A Address and Data Bus Signals The following paragraphs describe the Port A address and data bus signals. These pins are three-stated during reset and may require pullup resistors to prevent erroneous operation. MOTOROLA PORT A 8 - 5...
Page 177 X, Y, P, and I/O. The second method uses the bus strobe/wait (BS/ 8 - 6 PORT A MOTOROLA...
Page 178 BCR to insert up to15 wait states if it is known ahead of time that access to slower mem- ory or I/O devices is required. A bus wait signal allows an external device to control the number of wait states (not limited to 15) inserted in a bus access operation. MOTOROLA PORT A 8 - 7...
Page 179 PORT A INTERFACE 8 - 8 PORT A MOTOROLA...
Page 180: Pll Clock Oscillator
SECTION 9 PLL CLOCK OSCILLATOR Φ ∫ x x d MOTOROLA PLL CLOCK OSCILLATOR 9 - 1...
Page 181: Pll Components
9.4.5 Change of DF0-DF3 Bits ..............13 9.4.6 Loss of Lock ..................13 9.4.7 STOP Processing State ..............13 9.4.8 CKOUT Considerations ..............14 9.4.9 Synchronization Among EXTAL, CKOUT, and the Internal Clock ..14 9 - 2 PLL CLOCK OSCILLATOR MOTOROLA...
Page 182: Pll Clock Oscillator Introduction
PLL CLOCK OSCILLATOR INTRODUCTION PLL CLOCK OSCILLATOR INTRODUCTION The DSP56K family of processors (with the exception of the DSP56000 and DSP56001) features a PLL (phase-locked loop) clock oscillator in its central processing module, shown in Figure 9-2. The PLL allows the processor to operate at a high internal clock fre- quency using a low frequency clock input, a feature which offers two immediate benefits.
Page 183: Section 9.2 Pll Components
(EXTAL) and an internal clock phase from the frequency multiplier. At the point where there is negligible phase difference and the frequency of the two inputs is identical, the PLL is in the “locked” state. 9 - 4 PLL CLOCK OSCILLATOR MOTOROLA...
Page 184: Voltage Controlled Oscillator (Vco)
PCTL Multiplication Factor Bits (MF0-MF11) - Bits 0-11 The Multiplication Factor Bits MF0-MF11 define the multiplication factor (MF) that will be applied to the PLL input frequency. The MF can be any integer from 1 to 4096. Table 9-1 MOTOROLA PLL CLOCK OSCILLATOR 9 - 5...
Page 185: Division Factor Bits Df0-Df3
The Division Factor Bits DF0-DF3 define the divide factor (DF) of the low power divider. These bits specify any power of two divide factor in the range from 2 to 2 . Table 9-2 9 - 6 PLL CLOCK OSCILLATOR MOTOROLA...
Page 186: Pctl Xtal Disable Bit (Xtld) - Bit 16
STOP state. When PSTP is cleared, the PLL and the on-chip crystal oscillator will be disabled when the chip enters the STOP processing. For minimal power consumption during the STOP state, at the cost of longer recovery time, PSTP should be MOTOROLA PLL CLOCK OSCILLATOR 9 - 7...
Page 187: Pctl Pll Enable Bit (Pen) - Bit 18
If the programmer re-enables the CKOUT output before it reaches the high logic level during the disabling process, the CKOUT operation will be unaffected. The COD0-COD1 bits are cleared by hardware reset. 9 - 8 PLL CLOCK OSCILLATOR MOTOROLA...
Page 188: Pll Pins
GND dedicated to the analog PLL circuits. The pin should be provided with an extremely low impedance path to ground. PVCC should be bypassed to PGND µ by a 0.1 F capacitor located as close as possible to the chip package. MOTOROLA PLL CLOCK OSCILLATOR 9 - 9...
Page 189 PLOCK is asserted if the PLL is disabled. PLOCK is a reliable indicator of the PLL lock state only after exiting the hardware reset state. 9 - 10 PLL CLOCK OSCILLATOR MOTOROLA...
Page 190: Pll Operation Considerations
PEN bit is cleared, the PLL is deactivated and the internal chip clock is driven by the EXTAL pin. 3. PLOCK is a reliable indicator of the PLL lock state only after exiting the hard- ware reset state. MOTOROLA PLL CLOCK OSCILLATOR 9 - 11...
Page 191: Operation With Pll Disabled
For MF changing DF0-DF3 may lengthen the instruction cycle or CKOUT pulse following the PLL control register update in order to keep synchronization between EXTAL and the internal 9 - 12 PLL CLOCK OSCILLATOR MOTOROLA...
Page 192: Loss Of Lock
CKOUT clock output will complete the low cycle and then be disabled high. If the programmer re-enables the CKOUT clock output before it reaches the high logic level dur- ing the disabling process, the CKOUT operation will be unaffected. MOTOROLA PLL CLOCK OSCILLATOR 9 - 13...
Page 193: Synchronization Among Extal, Ckout, And The Internal Clock
Low clock skew between EXTAL and CKOUT is guaranteed only if MF 4. The synchro- nization between CKOUT and the internal chip activity and Port A timing is guaranteed in all cases where CKOS=CSRC and the bits have never differed from one another. 9 - 14 PLL CLOCK OSCILLATOR MOTOROLA...
Page 194: On-Chip Emulation (Once)
SECTION 10 ON-CHIP EMULATION (OnCE) 10- 2 ON-CHIP EMULATION (OnCE) MOTOROLA...
Page 195 SECTION 10.7 PIPELINE INFORMATION AND GLOBAL DATA BUS REGISTER ...............16 SECTION 10.8 PROGRAM ADDRESS BUS HISTORY BUFFER ....18 SECTION 10.9 SERIAL PROTOCOL DESCRIPTION ........19 SECTION 10.10 DSP56K TARGET SITE DEBUG SYSTEM REQUIREMENTS ..............19 SECTION 10.11 USING THE OnCE ..............20 10 - 3 ON-CHIP EMULATION (OnCE) MOTOROLA...
Page 196: On-Chip Emulation Introduction
DSCK serial clock (described in Section 10.2.2). Data is always shifted into the OnCE serial port most significant bit (MSB) first. When the DSI/OS0 pin is an output, it works in conjunction with the OS1 pin to provide chip status information (see Table 10-1). The 10- 4 ON-CHIP EMULATION (OnCE) MOTOROLA...
Page 197: Dsp56K Block Diagram
During hardware reset, this pin is defined as an out- put and it is driven low. Note: To avoid possible glitches, an external pull-down resistor should be attached to this pin. MOTOROLA ON-CHIP EMULATION (OnCE) 10 - 5...
Page 198: Chip Status Information
DSO pin will be pulsed low to indicate that the OnCE serial port is ready to receive the data to be written; after the data is written, another acknowledge pulse will be provided. During hardware reset and when the processor is idle, the DSO pin is held high. 10- 6 ON-CHIP EMULATION (OnCE) MOTOROLA...
Page 199: Once Controller And Serial Interface
OnCE COMMAND REGISTER DSCK ISBKPT BIT 7 BIT COUNTER ISTRACE OnCE DECODER BIT 23 ISDR ISDEBUG ISSWDBG STATUS AND CONTROL REGISTER REG READ REG WRITE MODE SELECT Figure 10-3 OnCE Controller and Serial Interface MOTOROLA ON-CHIP EMULATION (OnCE) 10 - 7...
Page 200: Once Command Register
Clear Trace Counter (OTC) 01111 Reserved 10000 Reserved 10001 Program Address Bus FIFO and Increment Counter 10010 Reserved 10011 PAB Register for Decode (OPABDR) 101xx Reserved 11xx0 Reserved 11x0x Reserved 110xx Reserved 11111 No Register Selected 10- 8 ON-CHIP EMULATION (OnCE) MOTOROLA...
Page 201 DSCK. The OBC is cleared during hardware reset and whenever the DSP56K acknowledges that the debug mode has been entered. The OBC supplies two signals to the OnCE Decoder: one indicating that the first 8 bits were MOTOROLA ON-CHIP EMULATION (OnCE) 10 - 9...
Page 202: Once Status And Control Register (Oscr)
Explicit program memory write accesses resulting from MOVEP and MOVEM instructions to P: memory space are ignored..* Reserved, read as zero, should be written with zero for future compatibility. Figure 10-5 OnCE Status and Control Register (OSCR) 10- 10 ON-CHIP EMULATION (OnCE) MOTOROLA...
Page 203: Memory Breakpoint Control Table
The TME control bit, when set, enables the Trace Mode of operation (see Section 10.5). This bit is cleared on hardware reset. 10.3.4.3 Reserved (Bits 5-7, 11-15) These bits are reserved for future use. They read as zero and should be written with zero for future compatibility. MOTOROLA ON-CHIP EMULATION (OnCE) 10 - 11...
Page 204: Once Memory Breakpoint Logic
(ISBKPT asserted). 10.4.1 Memory Address Latch (OMAL) The Memory Address Latch is a 16-bit register that latches the PAB, XAB or YAB on every instruction cycle according to the BC3-BC0 bits in OSCR. 10- 12 ON-CHIP EMULATION (OnCE) MOTOROLA...
Page 205: Once Memory Breakpoint Logic
10.4.3 Memory Lower Limit Register (OMLLR) The 16-bit Memory Lower Limit Register stores the memory breakpoint lower limit. The OMLLR can be read or written through the OnCE serial interface. Before enabling break- MOTOROLA ON-CHIP EMULATION (OnCE) 10 - 13...
Page 206: Once Trace Logic
(The OnCE trace logic is independent of the trace facility of the DSP56000/56001, which is operated through the trace interrupt discussed in Section 7.3.3.3, and started by setting the trace bit in the processor’s status register discussed in Section 5.4.2.12).
Page 207: Once Trace Logic Block Diagram
The OTC is a 24-bit counter that can be read, written, or cleared through the OnCE serial interface. If N instructions are to be executed before entering the debug mode, the Trace Counter should be loaded with N-1. The Trace Counter is cleared by hardware reset. MOTOROLA ON-CHIP EMULATION (OnCE) 10 - 15...
Page 208: Methods Of Entering The Debug Mode
DR before sending the first command. Note that in this case, the chip completes the execution of the WAIT instruction and halts after the next instruction enters the instruction latch. 10- 16 ON-CHIP EMULATION (OnCE) MOTOROLA...
Page 209: Pipeline Information And Global Data Bus Register
OPDBR can be read or written through the OnCE serial interface. It is affected by the op- erations performed during the debug mode and must be restored by the external com- mand controller when the chip returns to normal mode. MOTOROLA ON-CHIP EMULATION (OnCE) 10 - 17...
Page 210: Program Address Bus History Buffer
OPABDR tells which opcode is in the decode stage. To ease debug- ging activity and keep track of program flow, a First-In-First-Out (FIFO) buffer stores the DSCK GDB REGISTER (OGDBR) PDB REGISTER (OPDBR) PIL REGISTER (OPILR) Figure 10-8 OnCE Pipeline Information and GDB Registers 10- 18 ON-CHIP EMULATION (OnCE) MOTOROLA...
Page 211: Once Pab Fifo
The OPABDR is a 16-bit register that stores the address of the instruction currently in the instruction latch. This is the instruction that would have been decoded if the chip would not have entered the debug mode. OPABDR can only be read through the serial interface. MOTOROLA ON-CHIP EMULATION (OnCE) 10 - 19...
Page 212: Serial Protocol Description
(when the chip will receive data and write the data in one of the OnCE registers). • commands that do not have data transfers associated with them. The commands are 8 bits long and have the format shown in Figure 10-4. 10- 20 ON-CHIP EMULATION (OnCE) MOTOROLA...
Page 213: Dsp56K Target Site Debug System Requirements
3. Read PAB FIFO and fetch/decode info (this step is optional): a. Send command READ PAB address for fetch (10001010) b. ACK c. CLK d. Send command READ PAB address for decode (10010011) e. ACK MOTOROLA ON-CHIP EMULATION (OnCE) 10 - 21...
Page 214: Using The Once
GDB REGISTER. The signal that marks the end of the instruction returns the chip to the debug mode. 4. ACK 5. Send command READ GDB REGISTER (10001000) 10- 22 ON-CHIP EMULATION (OnCE) MOTOROLA...
Page 215 The OnCE controller selects PDB as destination for serial data. 13. ACK 14. Send the 24-bit 2 word of: “MOVE #$xxxx,R0” (the xxxx field). After 24 bits have been received, the PDB register drives the PDB. The OnCE con- MOTOROLA ON-CHIP EMULATION (OnCE) 10 - 23...
Page 216 OnCE controller selects PDB as destination for serial data. 31. ACK 32. Send the 24-bit DSP56K opcode: “MOVE #saved_r0,R0” After 24 bits have been received, the PDB register drives the PDB. The OnCE con- 10- 24 ON-CHIP EMULATION (OnCE) MOTOROLA...
Page 217 After 24 bits have been received, the PDB register drives the PDB. The OnCE con- troller releases the chip from the debug mode and the instruction starts execution. The signal that marks the end of the instruction returns the chip to the debug mode. 37. ACK MOTOROLA ON-CHIP EMULATION (OnCE) 10 - 25...
Page 218 There are two cases for returning from the debug mode in a single processor: • Control is returned to the program that was running before debug was initiated. • Jump to a different program location is executed. 10- 26 ON-CHIP EMULATION (OnCE) MOTOROLA...
Page 219 7. Send 24 bits of the jump target absolute address ($xxxxxx). After 24 bits have been received, the PDB register drives the PDB. In this way, the PDB contains the second word of the jump as required for the jump instruction ex- MOTOROLA ON-CHIP EMULATION (OnCE) 10 - 27...
Page 220 9. Send command NO REGISTER SELECTED, GO, EX (01111111) The OnCE controller releases the chips from the debug mode and instruction exe- cution is resumed. 10- 28 ON-CHIP EMULATION (OnCE) MOTOROLA...
Page 221 USING THE OnCE MOTOROLA ON-CHIP EMULATION (OnCE) 10 - 29...
Page 222 Transforms: Filters: Floating-Point Motorola Routines: Functions: Lattice Filters: Matrix Operations: Reed-Solomon Encoder: Sorting Routines: Speech: Standard I/O Equates: Tools and Utilities: Motorola DSP Product Support DSP56000CLASx Assembler/Simulator C Language Compiler DSP56000ADSx Application Development System MOTOROLA ADDITIONAL SUPPORT 11 - 1...
Page 223 SECTION CONTENTS SECTION 11.1 USER SUPPORT ..............3 SECTION 11.2 MOTOROLA DSP PRODUCT SUPPORT .......4 11.2.1 DSP56000CLASx Assembler/Simulator ...........4 11.2.2 Macro Cross Assembler Features: ............4 11.2.3 Simulator Features: ................5 11.2.4 DSP56KCCx Language Compiler Features: ........5 SECTION 11.3 DSP56KADSx APPLICATION DEVELOPMENT SYSTEM ..6 11.3.1 DSP56KADS Application Development...
Page 224: Additional Support
USER SUPPORT 11.1 USER SUPPORT User support from the conception of a design through completion is available from Motorola and third-party companies as shown in the following list: Motorola Third Party Design Data Sheets Data Acquisition Packages Application Notes Filter Design Packages...
Page 225: Motorola Dsp Product Support
MOTOROLA DSP PRODUCT SUPPORT The following is a partial list of the support available for the DSP56000/DSP56001. Addi- tional information can be obtained through Dr. BuB or the appropriate support telephone service. 11.2 MOTOROLA DSP PRODUCT SUPPORT • DSP56000CLASx Design-In Software Package which includes:...
Page 226: Simulator Features
MOTOROLA DSP PRODUCT SUPPORT the DSP56K family of processors • Modular programming features: local labels, sections, and external deﬁnition/ref- erence directives • Nested macro processing capability with support for macro libraries • Complex expression evaluation including boolean operators • Built-in functions for data conversion, string comparison, and common transcen- dental math functions •...
Page 227: Dsp56Kadsx Application Development System
• Host operating system commands from within ADS user interface program • Multiple OS I/O ﬁle access from DSP56K object programs • Fully compatible with the DSP56KCLASx design-in software package • On-line help screens for each command and DSP56K register 11 - 6 ADDITIONAL SUPPORT MOTOROLA...
Page 228: Dr. Bub Electronic Bulletin Board
Dr. BuB is an electronic bulletin board which provides free source code for a large variety of topics that can be used to develop applications with Motorola DSP products. The soft- ware library contains files including FFTs, FIR filters, IIR filters, lattice filters, matrix alge- bra routines, companding routines, floating-point routines, and others.
Page 229 Memory for multichannel DTMF routine dtmftwo.asm 10256 ex56.bat genxd.lod Data file genyd.lod Data file goertzel.asm Goertzel routine 4393 goertzel.lnk Link file for Goertzel routine 6954 goertzel.lst List file for Goertzel routine 11600 load.cmd tstgoert.mem Memory for Goertzel routine 11 - 8 ADDITIONAL SUPPORT MOTOROLA...
Page 230 Discrete Cosine Transform using FFT 5493 dct1.hlp Help file for dct1.asm fftr2cc.asm Radix 2, In-place Decimation-in-time 6524 complex FFT macro fftr2cc.hlp Help file for fftr2cc.asm 3533 fftr2cn.asm Radix 2, Decimation-in-time Complex FFT 6584 macro with normally ordered input/output MOTOROLA ADDITIONAL SUPPORT 11 - 9...
Page 231 Second Order Direct Canonic IIR Filter (Biquad IIR Filter) iir4.hlp Help for iir4.asm 2255 iir4t.asm Test program for iir4.asm 1202 iir5.asm Second Order Direct Canonic IIR Filter with Scaling (Biquad IIR Filter) iir5.hlp Help for iir5.asm 2803 11 - 10 ADDITIONAL SUPPORT MOTOROLA...
Page 232 Floating point negate 2026 fpabs.asm Floating point absolute value 1953 fpscale.asm Floating point scaling 2127 fpfix.asm Floating to fixed point conversion 3953 fpfloat.asm Fixed to floating point conversion 2053 fpceil.asm Floating point CEIL subroutine 1771 MOTOROLA ADDITIONAL SUPPORT 11 - 11...
Page 233 Test program for sqrt3.asm 1053 tli.asm Linear table lookup/interpolation 3253 routine for function generation tli.hlp Help for tli.asm 1510 bingray.asm Binary to Gray code conversion macro bingrayt.asm Test program for bingray.asm rand1.asm Pseudo Random Sequence Generator 2446 11 - 12 ADDITIONAL SUPPORT MOTOROLA...
Page 234 Help for matmul2.asm matmul3.asm General Matrix Multiply-Accumulate, 2815 C=AB+Q matmul3.hlp Help for matmul3.asm Reed-Solomon Encoder: readme.rs Instructions for Reed-Solomon coding 5200 rscd.asm Reed-Solomon coder for DSP56000 simulator 5822 newc.c Reed-Solomon coder coded in C 4075 MOTOROLA ADDITIONAL SUPPORT 11 - 13...
Page 235 Standard Interrupt Equate File 1082 intequlc.asm Lower Case Version of intequ.asm 1082 Tools and Utilities: srec.c 4.10 Utility to convert DSP56000 OMF format 38975 to SREC. srec.doc 4.10 Manual page for srec.c. 7951 srec.h 4.10 Include file for srec.c...
Page 236 Test program for parity.asm parityt.hlp Help for parityt.asm dspbug Ordering information for free debug monitor for DSP56000/DSP56001 The following is a list of current DSP56200 related software: Information on 56200 Filter Software 6343 Interrupt Driven Adaptive Filter Flowchart. 10916 “C”...
Page 237: Motorola Dsp News
11.5 MOTOROLA DSP NEWS The Motorola DSP News is a quarterly newsletter providing information on new products, application briefs, questions and answers, DSP product information, third-party product news, etc. This newsletter is free and is available upon request by calling the marketing information phone number listed below.
Page 238: Training Courses – (602) 897-3665 Or (800) 521-6274
TRAINING COURSES – (602) 897-3665 or (800) 521-6274 11.12 TRAINING COURSES – (602) 897-3665 or (800) 521-6274 There are two DSP56000 Family training courses available: 1. Introduction to the DSP5600X (MTTA5) is a 4.5-hour audio-tape course on the DSP56K Family architecture and programming.
Page 239: Section 11.13 Reference Books And Manuals
THEORY AND APPLICATION OF DIGITAL SIGNAL PROCESSING Rabiner, Lawrence R., Gold and Bernard Englewood Cliffs, NJ: Prentice-Hall, Inc., 1975 Digital Audio and Filters: ADAPTIVE FILTER AND EQUALIZERS B. Mulgrew and C. Cowan Higham, MA: Kluwer Academic Publishers, 1988 11 - 18 ADDITIONAL SUPPORT MOTOROLA...
Page 240 New York, NY: McGraw-Hill Company, Inc., 1988 INTRODUCTION TO ADAPTIVE FILTERS Simon Haykin New York, NY: MacMillan Publishing Company, 1984 MUSICAL APPLICATIONS OF MICROPROCESSORS (Second Edition) H. Chamberlin Hasbrouck Heights, NJ: Hayden Book Co., 1985 MOTOROLA ADDITIONAL SUPPORT 11 - 19...
Page 241 New York, NY: Holt, Reinholt, and Winston, Inc., 1980 DIGITAL CONTROL SYSTEM ANALYSIS & DESIGN C. Phillips and H. Nagle Englewood Cliffs, NJ: Prentice-Hall, Inc., 1984 ISSUES IMPLEMENTATION DIGITAL FEEDBACK COMPENSATORS P. Moroney Cambridge, MA: The MIT Press, 1983 11 - 20 ADDITIONAL SUPPORT MOTOROLA...
Page 242 William M. Newman and Roger F. Sproull New York, NY: McGraw-Hill Company, Inc., 1979 PROCEDURAL ELEMENTS FOR COMPUTER GRAPHICS David F. Rogers New York, NY: McGraw-Hill Company, Inc., 1985 RENDERMAN INTERFACE, THE Pixar San Rafael, CA. 94901 MOTOROLA ADDITIONAL SUPPORT 11 - 21...
Page 243 D. Saupe, and R. F. Voss New York, NY: Springer-Verlag Motorola DSP Manuals: MOTOROLA DSP56000 LINKER/LIBRARIAN REFERENCE MANUAL Motorola, Inc., 1991. MOTOROLA DSP56000 MACRO ASSEMBLER REFERENCE MANUAL Motorola, Inc., 1991. MOTOROLA DSP56000 SIMULATOR REFERENCE MANUAL Motorola, Inc., 1991. MOTOROLA DSP56000/DSP56001 USER’S MANUAL Motorola, Inc.,1990.
Page 244 DIGITAL CODING OF WAVEFORMS N. S. Jayant and P. Noll Englewood Cliffs, NJ: Prentice-Hall, Inc., 1984 DIGITAL PROCESSING OF SPEECH SIGNALS Lawrence R. Rabiner and R. W. Schafer Englwood Cliffs, NJ: Prentice-Hall, Inc., 1978 MOTOROLA ADDITIONAL SUPPORT 11 - 23...
Page 245 Reading, MA: Addison-Wesley Publishing Company, Inc., 1987 Telecommunications: DIGITAL COMMUNICATION Edward A. Lee and David G. Messerschmitt Higham, MA: Kluwer Academic Publishers, 1988 DIGITAL COMMUNICATIONS John G. Proakis New York, NY: McGraw-Hill Publishing Co., 1983 11 - 24 ADDITIONAL SUPPORT MOTOROLA...
Page 246 Transforms Filters Floating-Point Motorola Routines Functions Lattice Filters Matrix Operations Reed-Solomon Encoder Sorting Routines Speech Standard I/O Equates Tools and Utilities Motorola DSP Product Support DSP56100CLASx Assembler/Simulator C Language Compiler DSP56156ADSx Application Development System MOTOROLA ADDITIONAL SUPPORT 12 - 1...
Page 247 12.5 MOTOROLA DSP NEWS ........12-7 12.6 MOTOROLA FIELD APPLICATION ENGINEERS .
Page 248: Appendix A Introduction
INTRODUCTION 12.1 INTRODUCTION This section is intended as a guide to the DSP support services and products offered by Motorola. This includes training, development hardware and software tools, telephone support, etc. 12.2 THIRD PARTY SUPPORT User support from the conception of a design through completion is available from Motor-...
Page 249: Motorola Dsp Product Support
• Support Integrated Circuits • DSP Bulletin Board (Dr. BuB) • Motorola DSP Newsletter • Motorola Technical Service Engineers (TSEs) See your local telephone directory for the Motorola Semiconductor Sector sales ofﬁce telephone number. • Design Hotline • Applications Assistance •...
Page 250 12.3.2 Application Development Systems • Application Development Systems (ADS) are available for all family members. Up- grading an ADS to run a different Motorola DSP is done by purchasing and plug- ging in a new Application Development Module. MOTOROLA ADDITIONAL SUPPORT...
Page 251: Support Integrated Circuits
• Fully compatible with the DSP56100CLASx design-in software package • On-line help screens for each command and DSP561xx register 12.4 SUPPORT INTEGRATED CIRCUITS • DSP56ADC16 16-bit, 100-kHz analog-to-digital converter • DSP56401 AES/EBU processor • DSP56200 FIR ﬁlter 12 - 6 ADDITIONAL SUPPORT MOTOROLA...
Page 252: Motorola Dsp News
12.5 MOTOROLA DSP NEWS The Motorola DSP News is a quarterly newsletter providing information on new products, application briefs, questions and answers, DSP product information, third-party product news, etc. This newsletter is free and is available upon request by calling the marketing information phone number listed below.
Page 253: Dsp Training Courses - (602) 897-3665 Or (800) 521-6274
Dr. BuB is an electronic bulletin board providing free source code for a large variety of topics that can be used to develop applications with Motorola DSP products. The software library includes files including FFTs, FIR filters, IIR filters, lattice filters, matrix algebra routines, companding routines, floating-point routines, and others.
Page 254 Help for loglint.asm 1993 linlog.asm Linear PCM to companded CODEC data 4847 conversion linlog.hlp Help for linlog.asm 1714 12.13.4 DTMF Routines clear.cmd Explained in read.me file data.lod det.asm Subroutine used in IIR DTMF 5923 MOTOROLA ADDITIONAL SUPPORT 12 - 9...
Page 255 Help for fftr2b.asm 3680 fftr2c.asm Radix 2, In-Place, DIT FFT (even faster) 5991 fftr2c.hlp Help for fftr2c.asm 3231 fftr2d.asm Radix 2, In-Place, DIT FFT (using 3727 DSP56001 sine-cosine ROM tables) fftr2d.hlp Help for fftr2d.asm 3457 12 - 10 ADDITIONAL SUPPORT MOTOROLA...
Page 256 Test program for fir.asm 1164 iir1.asm Direct Form Second Order All Pole IIR Filter iir1.hlp Help for iir1.asm 1786 iir1t.asm Test program for iir1.asm 1157 iir2.asm Direct Form Second Order All Pole IIR Filter with Scaling MOTOROLA ADDITIONAL SUPPORT 12 - 11...
Page 257 Storage format and arithmetic 10600 representation definition fpcalls.hlp Subroutine calling conventions 11876 fplist.asm Test file that lists all subroutines 1601 fprevs.hlp Latest revisions of floating-point lib 1799 fpinit.asm Library initialization subroutine 2329 fpadd.asm Floating point add 3860 12 - 12 ADDITIONAL SUPPORT MOTOROLA...
Page 258 Exponential base 2 by polynomial approximation exp2.hlp Help for exp2.asm exp2t.asm Test program for exp2.asm 1019 sqrt1.asm Square Root by polynomial approximation, 7 bit accuracy sqrt1.hlp Help for sqrt1.asm sqrt1t.asm Test program for sqrt1.asm 1065 MOTOROLA ADDITIONAL SUPPORT 12 - 13...
Page 259 Generalized Lattice FIR/IIR 1334 Filter Macro latgen.hlp Help for latgen.asm 5485 latgent.asm Test program for latgen.asm 1269 latnrm.asm Normalized Lattice IIR Filter Macro 1407 latnrm.hlp Help for latnrm.asm 7475 latnrmt.asm Test program for latnrm.asm 1595 12 - 14 ADDITIONAL SUPPORT MOTOROLA...
Page 260 C=AB+Q matmul3.hlp Help for matmul3.asm 12.13.11 Reed-Solomon Encoder readme.rs Instructions for Reed-Solomon coding 5200 rscd.asm Reed-Solomon coder for DSP56000 simulator 5822 newc.c Reed-Solomon coder coded in C 4075 table1.asm Include file for R-S coder 7971 table2.asm Include file for R-S coder 4011 12.13.12 Sorting Routines...
Page 261 Standard Interrupt Equate File 1082 intequlc.asm Lower Case Version of intequ.asm 1082 12.13.15 Tools and Utilities srec.c 4.10 Utility to convert DSP56000 OMF format 38975 to SREC. srec.doc 4.10 Manual page for srec.c. 7951 srec.h 4.10 Include file for srec.c 3472 srec.exe...
Page 262: Reference Books And Manuals
David J. DeFatta, Joseph G. Lucas, and William S. Hodgkiss New York, NY: John Wiley and Sons, 1988 FOUNDATIONS OF DIGITAL SIGNAL PROCESSING AND DATA ANALYSIS J. A. Cadzow New York, NY: MacMillan Publishing Company, 1987 MOTOROLA ADDITIONAL SUPPORT 12 - 17...
Page 263 ART OF DIGITAL AUDIO, THE John Watkinson Stoneham. MA: Focal Press, 1988 DESIGNING DIGITAL FILTERS Charles S. Williams Englewood Cliffs, NJ: Prentice-Hall, Inc., 1986 DIGITAL AUDIO SIGNAL PROCESSING AN ANTHOLOGY John Strawn William Kaufmann, Inc., 1985 12 - 18 ADDITIONAL SUPPORT MOTOROLA...
Page 264 American National Standards Institute, inc., 1990 THE C PROGRAMMING LANGUAGE Brian W. Kernighan, and Dennis M. Ritchie Prentice-Hall, Inc., 1978. 12.14.4 Controls ADAPTIVE CONTROL K. Astrom and B. Wittenmark New York, NY: Addison-Welsey Publishing Company, Inc., 1989 MOTOROLA ADDITIONAL SUPPORT 12 - 19...
Page 265 New York, NY: John Wiley and Sons, Inc. GKS THEORY AND PRACTICE P. R. Bono and I. Herman (Eds.) New York, NY: Springer-Verlag, 1987 ILLUMINATION AND COLOR IN COMPUTER GENERATED IMAGERY Roy Hall New York, NY: Springer-Verlag 12 - 20 ADDITIONAL SUPPORT MOTOROLA...
Page 266 M. F. Barnsley, R. L. Devaney, B. B. Mandelbrot, H. O. Peitgen, D. Saupe, and R. F. Voss New York, NY: Springer-Verlag 12.14.7 Motorola DSP Manuals MOTOROLA DSP LINKER/LIBRARIAN REFERENCE MANUAL Motorola, Inc., 1992. MOTOROLA ADDITIONAL SUPPORT 12 - 21...
Page 267 REFERENCE BOOKS AND MANUALS MOTOROLA DSP ASSEMBLER REFERENCE MANUAL Motorola, Inc., 1992. MOTOROLA DSP SIMULATOR REFERENCE MANUAL Motorola, Inc., 1992. MOTOROLA DSP56000/DSP56001 USER’S MANUAL Motorola, Inc.,1990. MOTOROLA DSP56100 FAMILY MANUAL Motorola, Inc.,1992. MOTOROLA DSP56156 USER’S MANUAL Motorola, Inc.,1992. MOTOROLA DSP56166 USER’S MANUAL Motorola, Inc.,1992.
Page 268 New York, NY: Springer-Verlag, 1972 SPEECH COMMUNICATION – HUMAN AND MACHINE D. O’Shaughnessy Reading, MA: Addison-Wesley Publishing Company, Inc., 1987 12.14.11 Telecommunications DIGITAL COMMUNICATION Edward A. Lee and David G. Messerschmitt Higham, MA: Kluwer Academic Publishers, 1988 MOTOROLA ADDITIONAL SUPPORT 12 - 23...
Page 269 REFERENCE BOOKS AND MANUALS DIGITAL COMMUNICATIONS John G. Proakis New York, NY: McGraw-Hill Publishing Co., 1983 12 - 24 ADDITIONAL SUPPORT MOTOROLA...
Page 270 DO FOREVER CLR24 ENDDO TFR2 JScc BRKcc CMPM • Move TST2 ZERO DEC24 REPcc • Logical MOVE RESET MOVE(C) DMAC MOVE(I) ANDI MOVE(M) IMAC STOP MOVE(P) IMPY MOVE(S) WAIT INC24 MACR MPYR MPY(su,uu) MOTOROLA INSTRUCTION SET DETAILS A - 1...
Page 271: A.1 Appendix A Introduction
A.10.2 Instruction Encoding for the Parallel Move Portion of an Instruction ..............246 A.10.3 Instruction Encoding for Instructions Which Do Not Allow Parallel Moves .................248 A.10.4 Parallel Instruction Encoding of the Operation Code ......259 A - 2 INSTRUCTION SET DETAILS MOTOROLA...
Page 272: Instruction Guide
Those which are reserved are indicated with a double asterisk and are read as zeros. 6. Instruction Format: The instruction fields, the instruction opcode, and the instruc- tion extension word are specified for each instruction syntax. When the extension MOTOROLA INSTRUCTION SET DETAILS A - 3...
Page 273: Notation
Each instruction description contains symbols used to abbreviate certain operands and operations. Table A-1 lists the symbols used and their respective meanings. Depending on the context, registers refer to either the register itself or the contents of the register. A - 4 INSTRUCTION SET DETAILS MOTOROLA...
Page 274 When speciﬁed as a destination operand, sign extension and possibly zeroing are performed. Address ALU Registers Operands Address Registers R0 - R7 (16 Bits) Address Offset Registers N0 - N7 (16 Bits) Address Modiﬁer Registers M0 - M7 (16 Bits) MOTOROLA INSTRUCTION SET DETAILS A - 5...
Page 275 Absolute Short Address (6 Bits, Zero Extended) I/O Short Address (6 Bits, Ones Extended) <. . .> Speciﬁes the Contents of the Speciﬁed Address X Memory Reference Y Memory Reference Long Memory Reference = X:Y Program Memory Reference A - 6 INSTRUCTION SET DETAILS MOTOROLA...
Page 276 Absolute Value Operator Binary Operators Addition Operator Subtraction Operator Multiplication Operator ÷ Division Operator Logical Inclusive OR Operator • Logical AND Operator ⊕ Logical Exclusive OR Operator “Is Transferred To” Operator Concatenation Operator MOTOROLA INSTRUCTION SET DETAILS A - 7...
Page 277 Zero Bit Indicating if the A or B Result Equals Zero Overﬂow Bit Indicating if Arithmetic Overﬂow has Occurred in A or B Carry Bit Indicating if a Carry or Borrow Occurred in A or B Result A - 8 INSTRUCTION SET DETAILS MOTOROLA...
Page 278 Most Signiﬁcant Portion of a n Accumulator (A1 or B1) Rounding constant Shifting and/or Limiting on a Data ALU Register Sign Ext Sign Extension of a Data ALU Register Zero Zeroing of a Data ALU Register MOTOROLA INSTRUCTION SET DETAILS A - 9...
Page 279: Addressing Modes
Thus, memory alterable addressing modes use address register indirect and absolute addressing modes. A - 10 INSTRUCTION SET DETAILS MOTOROLA...
Page 280 Postincrement by 1 Postdecrement by 1 Postincrement by Offset Nn Postdecrement by Offset Nn Indexed by Offset Nn Predecrement by 1 Special Immediate Data Absolute Address Immediate Short Data Short Jump Address Absolute Short Address MOTOROLA INSTRUCTION SET DETAILS A - 11...
Page 281 – Used in instructions where two effective addresses are required. Memory Mode (M) – Refers to operands in memory using an effective addressing ﬁeld. Alterable Mode (A) – Refers to alterable or writable registers or memory. A - 12 INSTRUCTION SET DETAILS MOTOROLA...
Page 282: Addressing Mode Modifiers
Mn. The addressing mode update modifiers (M0–M7) are shown in Table A-4. There are no restrictions on the use of modifier types with any address register indirect addressing mode. MOTOROLA INSTRUCTION SET DETAILS A - 13...
Page 283 Multiple Wrap-Around Modulo 2 Reserved 1001 1111 1111 1111 9FFF Multiple Wrap-Around Modulo 2 Reserved 1011 1111 1111 1111 BFFF Multiple Wrap-Around Modulo 2 Reserved 1111 1111 1111 1111 FFFF Linear (Modulo 2 A - 14 INSTRUCTION SET DETAILS MOTOROLA...
Page 284: Condition Code Computation
CONTROL UNIT for information on the MR portion of the status register. The standard definition of the condition code bits follows. Exceptions to these stan- dard definitions are given in the notes which follow Table A-5. MOTOROLA INSTRUCTION SET DETAILS A - 15...
Page 285 The Block Floating Point FFT algorithm is described in the Motorola application note APR4/D, “Implemen- tation of Fast Fourier Transforms on Motorola’s DSP56000/ DSP56001 and DSP96002 Digital Signal Processors.” This bit is computed according to the logical equations below when an instruction or a parallel move moves the result of accumulator A or B to XDB or YDB.
Page 286 Set if an arithmetic overflow occurs in the 56-bit A or B result. This indicates that the result cannot be represented in the 56-bit accu- mulator; thus, the accumulator has overflowed. Cleared otherwise. MOTOROLA INSTRUCTION SET DETAILS A - 17...
Page 287 When using an optional parallel move, refer to the individual instruction’s detailed description in Section A.7 to see how the S and L bits are determined. A - 18 INSTRUCTION SET DETAILS MOTOROLA...
Page 288 — Not affected by the operation ? or # Set according to a special deﬁnition (refer to the following notes) and can be a 0 or 1 The following notes apply to Table A-5: MOTOROLA INSTRUCTION SET DETAILS A - 19...
Page 289: Parallel Move Descriptions
‘“parallel move)”. The MOVE instruction is equivalent to a NOP with paral- lel moves. Therefore, a detailed description of each parallel move is given with the MOVE instruction details in Section A.7, beginning on page A-160. A - 20 INSTRUCTION SET DETAILS MOTOROLA...
Page 290: Instruction Descriptions
MS 8, 9, or 10 bits of an accumulator. Refer to Section A.5 for complete details. MOTOROLA INSTRUCTION SET DETAILS A - 21...
Page 291 V — Set if overflow has occurred in A or B result Note: The definitions of the E and U bits vary according to the scaling mode being used. Refer to Section A.5 for complete details. A - 22 INSTRUCTION SET DETAILS MOTOROLA...
Page 292 INSTRUCTION DESCRIPTIONS Absolute Value Instruction Format: ABS D Opcode: DATA BUS MOVE FIELD OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 23...
Page 293: Adc
56 bits and the other 48-bit long-word operand is internally sign extended to 56 bits during instruction execution, the carry bit will be set correctly after the execution of the ADD X,A instruction. The ADC Y,B instruction then produces the correct MS 56-bit A - 24 INSTRUCTION SET DETAILS MOTOROLA...
Page 294 The definitions of the E and U bits vary according to the scaling mode being used. Refer to Section A.5 for complete details. Instruction Format: ADC S,D Opcode: DATA BUS MOVE FIELD OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 25...
Page 295: Add
B0) by loading the 24-bit operand into X0 or Y0, forming a 48-bit word by loading X1 or Y1 with the sign extension of X0 or Y0 and executing an ADD X,A or ADD Y,A instruc- tion. A - 26 INSTRUCTION SET DETAILS MOTOROLA...
Page 296 0 1 0 1 Y0,B 1 0 1 1 0 1 1 0 X1,A 1 1 0 0 0 1 1 1 X1,B 1 1 0 1 Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 27...
Page 297: Addl
$00:005000:000000. The ADDL A,B instruction adds two times the value in the B accu- mulator to the value in the A accumulator and stores the 56-bit result in the B accumula- tor. A - 28 INSTRUCTION SET DETAILS MOTOROLA...
Page 298 The definitions of the E and U bits vary according to the scaling mode being used. Refer to Section A.5 for complete details. Instruction Format: ADDL Opcode: DATA BUS MOVE FIELD OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 29...
Page 299: Addr
$80:000000:2468AC, and the 56-bit B accumulator contains the value $00:013570:000000. The ADDR B,A instruction adds one-half the value in the A accu- mulator to the value in the B accumulator and stores the 56-bit result in the A accumula- tor. A - 30 INSTRUCTION SET DETAILS MOTOROLA...
Page 300 The definitions of the E and U bits vary according to the scaling mode being used. Refer to Section A.5 for complete details. Instruction Format: ADDR S,D Opcode: DATA BUS MOVE FIELD OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 31...
Page 301: And
L — Set if limiting occurs during parallel move N — Set if bit 47 of A or B result is set Z— Set if bits 47–24 of A or B result are zero V — Always cleared A - 32 INSTRUCTION SET DETAILS MOTOROLA...
Page 302 AND S,D Opcode: DATA BUS MOVE FIELD OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: A 0 (only A1 is changed) B 1 (only B1 is changed) Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 33...
Page 303: Andi
$31. The AND #$FE,CCR instruction logically ANDs the immediate 8- bit value $FE with the contents of the condition code register and stores the result in the condition code register. A - 34 INSTRUCTION SET DETAILS MOTOROLA...
Page 304 Opcode: 16 15 Instruction Fields: #xx=8-bit Immediate Short Data — i i i i i i i i CCR 0 1 OMR 1 0 Timing: 2 oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 35...
Page 305: Asl
Explanation of Example: Prior to execution, the 56-bit A accumulator contains the value $A5:012345:012345. The execution of the ASL A instruction shifts the 56-bit value in the A accumulator one bit to the left and stores the result back in the A accumulator. A - 36 INSTRUCTION SET DETAILS MOTOROLA...
Page 306 The definitions of the E and U bits vary according to the scaling mode being used. Refer to Section A.5 for complete details. Instruction Format: Opcode: DATA BUS MOVE FIELD OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 37...
Page 307: Asr
Explanation of Example: Prior to execution, the 56-bit B accumulator contains the value $A8:A86420:A86421. The execution of the ASR B instruction shifts the 56-bit value in the B accumulator one bit to the right and stores the result back in the B accu- mulator. A - 38 INSTRUCTION SET DETAILS MOTOROLA...
Page 308 Note: The definitions of the E and U bits vary according to the scaling mode being used. Refer to Section A.5 for complete details. Instruction Format: Opcode: DATA BUS MOVE FIELD OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 39...
Page 309: Bchg
This instruction can use all memory alterable addressing modes. Example: BCHG #$7,X:<<$FFE2 ;test and change bit 7 in I/O Port B DDR Before Execution After Execution X:$FFE2 X;$FFE2 $000080 $000000 $0300 $0300 A - 40 INSTRUCTION SET DETAILS MOTOROLA...
Page 310 L — Set if data limiting has occurred. See Notes on page A-47. E — Not affected U — Not affected N — Not affected Z — Not affected V — Not affected C — Set if bit tested is set. Cleared otherwise. MOTOROLA INSTRUCTION SET DETAILS A - 41...
Page 311 — Changed if bit 15 is specified. Not affected otherwise. For other destination operands: — Not affected — Not affected S0 — Not affected S1 — Not affected — Not affected DM — Not affected — Not affected A - 42 INSTRUCTION SET DETAILS MOTOROLA...
Page 312 1 0 1 r r r -(Rn) 1 1 1 r r r Absolute address 1 1 0 0 0 0 where “rrr” refers to an address register R0-R7 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 43...
Page 313 Absolute Short Address=aaaaaa Absolute Short Address aaaaaa Memory SpaceS Bit Number bbbbb 000000 X Memory 00000 • • Y Memory • 10111 111111 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words A - 44 INSTRUCTION SET DETAILS MOTOROLA...
Page 314 I/O Short Address=pppppp I/O Short Address pppppp Memory SpaceS Bit Number bbbbb 000000 X Memory 00000 • • Y Memory • 10111 111111 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 45...
Page 315 0 1 1 N N N 8 address modifier registers in AGU 1 0 0 F F F 8 program controller registers 1 1 1 G G G See Section A.10 and Table A-18 for specific register encodings. A - 46 INSTRUCTION SET DETAILS MOTOROLA...
Page 316 5. The bit test and change is performed on A1 or B1, and the C bit is set if the bit tested is set. Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 47...
Page 317: Bclr
This instruction can use all memory alterable addressing modes. Example: BCLR #$E,X:<<$FFE4 ;test and clear bit 14 in I/O Port B Data Reg. Before Execution After Execution X:$FFE4 X:$FFE4 $FFFFFF $FFBFFF $0300 $0301 A - 48 INSTRUCTION SET DETAILS MOTOROLA...
Page 318 L — Set if data limiting has occurred. See Notes on page A-55. E — Not affected U — Not affected N — Not affected Z — Not affected V — Not affected C — Set if bit tested is set. Cleared otherwise. MOTOROLA INSTRUCTION SET DETAILS A - 49...
Page 319 — Cleared if bit 15 is specified. Not affected otherwise. For other destination operands: — Not affected — Not affected S0 — Not affected S1 — Not affected — Not affected DM — Not affected — Not affected A - 50 INSTRUCTION SET DETAILS MOTOROLA...
Page 320 1 0 1 r r r -(Rn) 1 1 1 r r r Absolute address 1 1 0 0 0 0 where “rrr” refers to an address register R0-R7 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 51...
Page 321 Absolute Short Address=aaaaaa Absolute Short Address aaaaaa Memory SpaceS Bit Number bbbbb 000000 X Memory 00000 • • Y Memory • 10111 111111 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words A - 52 INSTRUCTION SET DETAILS MOTOROLA...
Page 322 I/O Short Address=pppppp I/O Short Address pppppp Memory SpaceS Bit Number bbbbb 000000 X Memory 00000 • • Y Memory • 10111 111111 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 53...
Page 323 0 1 1 N N N 8 address modifier registers in AGU 1 0 0 F F F 8 program controller registers 1 1 1 G G G See Section A.10 and Table A-18 for specific register encodings. A - 54 INSTRUCTION SET DETAILS MOTOROLA...
Page 324 5. The bit test and clear is performed on A1 or B1, and the C bit is set if the bit tested is set. Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 55...
Page 325: Bset
This instruction can use all memory alterable addressing modes. Example: BSET #$0,X:<<$FFE5 ;test and clear bit 14 in I/O Port B Data Reg. Before Execution After Execution X:$FFE5 X:$FFE5 $000000 $000001 $0300 $0300 A - 56 INSTRUCTION SET DETAILS MOTOROLA...
Page 326 L — Set if data limiting has occurred. See Notes on page A-63. E — Not affected U — Not affected N — Not affected Z — Not affected V — Not affected C — Set if bit tested is set. Cleared otherwise. MOTOROLA INSTRUCTION SET DETAILS A - 57...
Page 327 — Set if bit 15 is specified. Not affected otherwise. For other destination operands: — Not affected — Not affected S0 — Not affected S1 — Not affected — Not affected DM — Not affected — Not affected A - 58 INSTRUCTION SET DETAILS MOTOROLA...
Page 328 1 0 1 r r r -(Rn) 1 1 1 r r r Absolute address 1 1 0 0 0 0 where “rrr” refers to an address register R0-R7 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 59...
Page 329 Absolute Short Address=aaaaaa Absolute Short Address aaaaaa Memory SpaceS Bit Number bbbbb 000000 X Memory 00000 • • Y Memory • 10111 111111 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words A - 60 INSTRUCTION SET DETAILS MOTOROLA...
Page 330 I/O Short Address=pppppp I/O Short Address pppppp Memory SpaceS Bit Number bbbbb 000000 X Memory 00000 • • Y Memory • 10111 111111 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 61...
Page 331 0 1 1 N N N 8 address modifier registers in AGU 1 0 0 F F F 8 program controller registers 1 1 1 G G G See Section A.10 and Table A-18 for specific register encodings. A - 62 INSTRUCTION SET DETAILS MOTOROLA...
Page 332 5. The bit test and set is performed on A1 or B1, and the C bit is set if the bit tested is set. Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 63...
Page 333: Btst
1st bit (serial input flag IF1) in X:$FFEE and sets the carry bit C accordingly. This instruction sequence illustrates serial to parallel conversion using the carry bit C and the 24-bit A1 register. A - 64 INSTRUCTION SET DETAILS MOTOROLA...
Page 334 L — Not affected S — Not affected MR Status bits are not affected. SP — Stack Pointer: For destination operand SSH: SP — Decrement by 1. For other destination operands: Not affected MOTOROLA INSTRUCTION SET DETAILS A - 65...
Page 335 1 0 1 r r r -(Rn) 1 1 1 r r r Absolute address 1 1 0 0 0 0 where “rrr” refers to an address register R0-R7 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words A - 66 INSTRUCTION SET DETAILS MOTOROLA...
Page 336 Absolute Short Address=aaaaaa Absolute Short Address aaaaaa Memory SpaceS Bit Number bbbbb 000000 X Memory 00000 • • Y Memory • 10111 111111 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 67...
Page 337 I/O Short Address=pppppp I/O Short Address pppppp Memory SpaceS Bit Number bbbbb 000000 X Memory 00000 • • Y Memory • 10111 111111 Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words A - 68 INSTRUCTION SET DETAILS MOTOROLA...
Page 338 4. The bit test is performed on the resulting 24-bit value and the C bit is set if the bit tested is set. The original contents of A or B are not changed. Timing: 4+mvb oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 69...
Page 339: Clr
S — Computed according to the definition in A.5 CONDITION CODE COMPUTATION L — Set if data limiting has occurred during parallel move E — Always cleared U — Always set N — Always cleared Z— Always set V — Always cleared A - 70 INSTRUCTION SET DETAILS MOTOROLA...
Page 340 INSTRUCTION DESCRIPTIONS Clear Accumulator Instruction Format: Opcode: DATA BUS MOVE FIELD OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 71...
Page 341 CMP Y0,B instruction automatically appends the 24-bit value in the Y0 register with 24 LS zeros, sign extends the resulting 48-bit long word to 56 bits, subtracts the result from the 56-bit B accumulator and updates the condition code register. A - 72 INSTRUCTION SET DETAILS MOTOROLA...
Page 342 1 1 0 1 X0,B 1 0 0 1 Y1,A 1 1 1 0 Y0,A 1 0 1 0 Y1,B 1 1 1 1 Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 73...
Page 343: Cmpm
24 LS zeros, sign extends the resulting 48-bit long word to 56 bits, takes the absolute value of the resulting 56-bit number, subtracts the result from the absolute value of the contents of the 56-bit A accumulator, and updates the condition code regis- ter. A - 74 INSTRUCTION SET DETAILS MOTOROLA...
Page 344 X1,B 1 1 0 1 X0,A 1 0 0 0 Y0,B 1 0 1 1 Y1,A 1 1 1 0 Y1,B 1 1 1 1 Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 75...
Page 345: Debug
DSO line. This informs the external command controller that the chip has entered the debug mode and is waiting for commands. Condition Codes: The condition codes are not affected by this instruction Instruction Format: DEBUG A - 76 INSTRUCTION SET DETAILS MOTOROLA...
Page 346 INSTRUCTION DESCRIPTIONS DEBUG DEBUG Enter Debug Mode Opcode: 16 15 Timing: 4 oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 77...
Page 347: Debugcc
U denotes the logical complement of U, denotes the logical OR operator, • denotes the logical AND operator, and ⊕ denotes the logical Exclusive OR operator Condition Codes: The condition codes are not affected by this instruction. A - 78 INSTRUCTION SET DETAILS MOTOROLA...
Page 348 1 1 0 0 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 Timing: 4 oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 79...
Page 349: Dec
N — Set if bit 55 of result is set Z — Set if result equals zero V — Set if overflow has occurred in result C — Set if a borrow occurs from bit 55 of result A - 80 INSTRUCTION SET DETAILS MOTOROLA...
Page 350 INSTRUCTION DESCRIPTIONS Decrement by One Instruction Format: Opcode: 16 15 Instruction Fields: Timing: 2 oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 81...
Page 351: Div
|D| < |S| and the operands are interpreted as fractions. Note that this condition ensures that the magnitude of the quotient is less than one (i.e., is fractional) and pre- cludes division by zero. A - 82 INSTRUCTION SET DETAILS MOTOROLA...
Page 352 S is subtracted from the accumulator. Due to the automatic sign extension of the 24-bit signed divisor, the addition or subtraction opera- tion correctly sets the carry bit C of the condition code register with the next quotient bit. MOTOROLA INSTRUCTION SET DETAILS A - 83...
Page 353 A1. This produces the correct LS 24 bits of the 48-bit signed remained in the 24-bit B1 register. Note that the remainder is really a 48-bit value which has 24 bits of precision. Thus, the correct 48-bit remainder is $000000:000100 which equals 0.0000000000018190 approximately. A - 84 INSTRUCTION SET DETAILS MOTOROLA...
Page 354 2. the number of bits of precision N in the quotient; 3. whether the value of N is fixed or is variable; 4. whether the operands are unsigned or signed; 5. whether or not the remainder is to be calculated. MOTOROLA INSTRUCTION SET DETAILS A - 85...
Page 355 V — Set if the MS bit of the destination operand is changed as a result of the instruction’s left shift operation C — Set if bit 55 of the result is cleared. A - 86 INSTRUCTION SET DETAILS MOTOROLA...
Page 356 X0,B 0 0 1 X1,B 1 0 1 Y0,A 0 1 0 Y1,A 1 1 0 Y0,B 0 1 1 Y1,B 1 1 1 Timing: 2 oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 87...
Page 357 DO loop will be executed and can be accessed from inside the DO loop subject to certain restrictions. If LC equals zero, the DO loop is A - 88 INSTRUCTION SET DETAILS MOTOROLA...
Page 358 (SSH) of (SP–1), the contents of the loop counter (LC) are restored from the lower portion (SSL) of (SP–1) and the stack pointer (SP) is decre- mented by two. Instruction fetches now continue at the address of the instruction follow- MOTOROLA INSTRUCTION SET DETAILS A - 89...
Page 359 MOVEP to LA, LC, SR, SP, SSH, or SSL ANDI MR ORI MR Two-word instructions which read LC, SP, or SSL At LA–1 Single-word instructions (except REP) which read LC, SP, or SSL, JCLR, JSET, two-word JMP, two-word Jcc A - 90 INSTRUCTION SET DETAILS MOTOROLA...
Page 360 MOVEC to LA, LC, SSH, SSL, or SP MOVEM to LA, LC, SSH, SSL, or SP MOVEP to LA, LC, SSH, SSL, or SP MOVEC from SSH MOVEM from SSH MOVEP from SSH MOTOROLA INSTRUCTION SET DETAILS A - 91...
Page 361 S — Computed according to the definition. See Notes on page A-97. L — Set if data limiting occurred. See Notes on page A-97. For other source operands: LF — Set when a DO loop is in progress A - 92 INSTRUCTION SET DETAILS MOTOROLA...
Page 362 1 0 0 r r r (Rn+Nn) 1 0 1 r r r -(Rn) 1 1 1 r r r where “rrr” refers to an address register R0-R7 Timing: 6+mv oscillator clock cycles Memory: 2 program words MOTOROLA INSTRUCTION SET DETAILS A - 93...
Page 363 Effective Short Address=aaaaaa, expr=16-bit Absolute Address in 24-bit extension word Absolute Short Address aaaaaa Memory SpaceS 000000 X Memory • Y Memory • 111111 Timing: 6+mv oscillator clock cycles Memory: 2 program words A - 94 INSTRUCTION SET DETAILS MOTOROLA...
Page 364 #xxx=12-bit Immediate Short Data = hhhhiiiiiiii, expr=16-bit Absolute Address in 24-bit extension word Immediate Short Data hhhh i i i i i i i i 000000000000 • • 111111111111 Timing: 6+mv oscillator clock cycles Memory: 2 program words MOTOROLA INSTRUCTION SET DETAILS A - 95...
Page 365 Thus, if SP=3, the execution of the DO SP,expr instruction will load the loop counter (LC) with the value LC=4. **For DO SSL, expr The loop counter (LC) will be loaded with its previous value which was saved on the stack by the DO instruction itself. A - 96 INSTRUCTION SET DETAILS MOTOROLA...
Page 366 4. The LS 16 bits of the resulting 24 bit value is loaded into the loop counter (LC). The original contents of A or B are not changed. Timing: 6+mv oscillator clock cycles Memory: 2 program words MOTOROLA INSTRUCTION SET DETAILS A - 97...
Page 367: Enddo
;LC equal to Y1, restore all DO registers JMP NEXT ;go to NEXT ONWARD ;LC not equal to Y1, continue DO loop ;(last instruction in DO loop) NEXT MOVE #$123456,X1 ;(first instruction AFTER DO loop) A - 98 INSTRUCTION SET DETAILS MOTOROLA...
Page 368 DO loop. Condition Codes: The condition codes are not affected by this instruction. Instruction Format: ENDDO Opcode: 16 15 Instruction Fields: None Timing: 2 oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 99...
Page 369: Eor
L — Set if data limiting has occurred during parallel move N — Set if bit 47 of A or B result is set Z— Set if bits 47 - 24 of A or B result are zero V — Always cleared A - 100 INSTRUCTION SET DETAILS MOTOROLA...
Page 370 EOR S,D Opcode: DATA BUS MOVE FIELD OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: X0 0 0 X1 1 0 Y0 0 1 Y1 1 1 Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 101...
Page 371: Illegal
Of course, the ILLEGAL interrupt service routine should abort further processing, and the processor should be reinitialized. Example: ILLEGAL ;begin ILLEGAL exception processing Explanation of Example: The ILLEGAL instruction suspends normal instruction execu- tion and initiates ILLEGAL exception processing. A - 102 INSTRUCTION SET DETAILS MOTOROLA...
Page 372 ILLEGAL Illegal Instruction Interrupt Condition Codes: The condition codes are not affected by this instruction. Instruction Format: ILLEGAL Opcode: 16 15 Instruction Fields: None Timing: 8 oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 103...
Page 373 Z — Set if A or B result equals zero V — Set if overflow has occurred in A or B result C — Set if a carry is generated from bit 55 of A or B result A - 104 INSTRUCTION SET DETAILS MOTOROLA...
Page 374 INSTRUCTION DESCRIPTIONS Increment by One Instruction Format: Opcode: 16 15 Instruction Fields: Timing: 2 oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 105...
Page 375 • — not normalized Z+(U E)=0 where U denotes the logical complement of U, denotes the logical OR operator, • denotes the logical AND operator, and ⊕ denotes the logical Exclusive OR operator A - 106 INSTRUCTION SET DETAILS MOTOROLA...
Page 376 (PC) if the specified condition is true. If the specified condition is not true, no jump is taken, and the program counter is incremented by one. Condition Codes: The condition codes are not affected by this instruction. Instruction Format: Opcode: 16 15 MOTOROLA INSTRUCTION SET DETAILS A - 107...
Page 377 1 1 1 0 1 1 1 1 1 1 1 Timing: 4+jx oscillator clock cycles Memory: 1+ea program words Instruction Format: Opcode: OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: cc=4-bit condition code=CCCC, ea=6-bit Effective Address=MMMRRR A - 108 INSTRUCTION SET DETAILS MOTOROLA...
Page 378 1 1 0 0 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 Timing: 4+jx oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 109...
Page 379 All address reg- ister indirect addressing modes may be used to reference the source operand S. Abso- lute Short and I/O Short addressing modes may also be used. A - 110 INSTRUCTION SET DETAILS MOTOROLA...
Page 380 E — Not affected U — Not affected N — Not affected Z — Not affected V — Not affected C — Not affected For other source operands: The condition codes are not affected. MOTOROLA INSTRUCTION SET DETAILS A - 111...
Page 381 1 0 0 r r r 10111 (Rn+Nn) 1 0 1 r r r -(Rn) 1 1 1 r r r where “rrr” refers to an address register R0-R7 Timing: 6+jx oscillator clock cycles Memory: 2 program words A - 112 INSTRUCTION SET DETAILS MOTOROLA...
Page 382 Absolute Address in extension word Absolute Short Address aaaaaa Memory SpaceS Bit Number bbbbb 000000 X Memory 00000 • • Y Memory • 10111 111111 Timing: 6+jx oscillator clock cycles Memory: 2 program words MOTOROLA INSTRUCTION SET DETAILS A - 113...
Page 383 Absolute Address in extension word I/O Short Address pppppp Memory SpaceS Bit Number bbbbb 000000 X Memory 00000 • • Y Memory • 10111 111111 Timing: 6+jx oscillator clock cycles Memory: 2 program words A - 114 INSTRUCTION SET DETAILS MOTOROLA...
Page 384 4. The bit test is performed on the resulting 24-bit value, and the jump is taken if the bit tested is clear. The original contents of A or B are not changed. Timing: 6+jx oscillator clock cycles Memory: 2 program words MOTOROLA INSTRUCTION SET DETAILS A - 115...
Page 385: Jmp
Explanation of Example: In this example, program execution is transferred to the pro- gram address P:(R1+N1). Condition Codes: The condition codes are not affected by this instruction. Instruction Format: JMP xxx Opcode: 16 15 A - 116 INSTRUCTION SET DETAILS MOTOROLA...
Page 386 1 0 1 r r r -(Rn) 1 1 1 r r r Absolute address 1 1 0 0 0 0 where “rrr” refers to an address register R0-R7 Timing: 4+jx oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 117...
Page 387: Jscc
⊕ — less than or equal Z+(N V)=1 — limit set ⊕ — less than — minus — not equal • E)=1 — normalized Z+(U — plus • — not normalized Z+(U E)=0 A - 118 INSTRUCTION SET DETAILS MOTOROLA...
Page 388 If the specified condition is not true, no jump is taken and the program counter is incremented by 1. Condition Codes: The condition codes are not affected by this instruction. MOTOROLA INSTRUCTION SET DETAILS A - 119...
Page 389 1 1 0 0 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 Timing: 4+jx oscillator clock cycles Memory: 1+ea program words A - 120 INSTRUCTION SET DETAILS MOTOROLA...
Page 390 Absolute address 1 1 0 0 0 0 0 1 1 1 1 1 1 1 where “rrr” refers to an address register R0–R7 Timing: 4+jx oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 121...
Page 391 Program execution then continues at the specified absolute address in the instruc- tion’s 24-bit extension word. If the specified memory bit is not clear, the program counter (PC) is incremented and the extension word is ignored. However, the address register A - 122 INSTRUCTION SET DETAILS MOTOROLA...
Page 392: Jsclr
P:$1357 in program memory if bit 1 of the external I/O loca- tion Y:<<$FFE3 is a zero. If the specified bit is not clear, no jump is taken and the program counter (PC) is incremented by 1. MOTOROLA INSTRUCTION SET DETAILS A - 123...
Page 393 E — Not affected U — Not affected N — Not affected Z — Not affected V — Not affected C — Not affected For other source operands: The condition codes are not affected. A - 124 INSTRUCTION SET DETAILS MOTOROLA...
Page 394 1 0 0 r r r 10111 (Rn+Nn) 1 0 1 r r r -(Rn) 1 1 1 r r r where “rrr” refers to an address register R0-R7 Timing: 6+jx oscillator clock cycles Memory: 2 program words MOTOROLA INSTRUCTION SET DETAILS A - 125...
Page 395 Absolute Address in extension word Absolute Short Address aaaaaa Memory SpaceS Bit Number bbbbb 000000 X Memory 00000 • • Y Memory • 10111 111111 Timing: 6+jx oscillator clock cycles Memory: 2 program words A - 126 INSTRUCTION SET DETAILS MOTOROLA...
Page 396 Absolute Address in extension word I/O Short Address aaaaaa Memory SpaceS Bit Number bbbbb 000000 X Memory 00000 • • Y Memory • 10111 111111 Timing: 6+jx oscillator clock cycles Memory: 2 program words MOTOROLA INSTRUCTION SET DETAILS A - 127...
Page 397 0 1 1 N N N 8 address modifier registers in AGU 1 0 0 F F F 8 program controller registers 1 1 1 G G G See Section A.10 and Table A-18 for specific register encodings. A - 128 INSTRUCTION SET DETAILS MOTOROLA...
Page 398 4. The bit test is performed on the resulting 24-bit value, and the jump to sub- routine is taken if the bit tested is clear. The original contents of A or B are not changed. Timing: 6+jx oscillator clock cycles Memory: 2 program words MOTOROLA INSTRUCTION SET DETAILS A - 129...
Page 399: Jset
All address reg- ister indirect addressing modes may be used to reference the source operand S. Abso- lute short and I/O short addressing modes may also be used. A - 130 INSTRUCTION SET DETAILS MOTOROLA...
Page 400 E — Not affected U — Not affected N — Not affected Z — Not affected V — Not affected C — Not affected For other source operands: The condition codes are not affected. MOTOROLA INSTRUCTION SET DETAILS A - 131...
Page 401 1 0 0 r r r 10111 (Rn+Nn) 1 0 1 r r r -(Rn) 1 1 1 r r r where “rrr” refers to an address register R0-R7 Timing: 6+jx oscillator clock cycles Memory: 2 program words A - 132 INSTRUCTION SET DETAILS MOTOROLA...
Page 402 Absolute Address in extension word Absolute Short Address aaaaaa Memory SpaceS Bit Number bbbbb 000000 X Memory 00000 • • Y Memory • 10111 111111 Timing: 6+jx oscillator clock cycles Memory: 2 program words MOTOROLA INSTRUCTION SET DETAILS A - 133...
Page 403 Absolute Address in extension word I/O Short Address pppppp Memory SpaceS Bit Number bbbbb 000000 X Memory 00000 • • Y Memory • 10111 111111 Timing: 6+jx oscillator clock cycles Memory: 2 program words A - 134 INSTRUCTION SET DETAILS MOTOROLA...
Page 404 4. The bit test is performed on the resulting 24-bit value, and the jump is taken if the bit tested is set. The original contents of A or B are not changed. Timing: 6+jx oscillator clock cycles Memory: 2 program words MOTOROLA INSTRUCTION SET DETAILS A - 135...
Page 405: Jsr
Explanation of Example: In this example, program execution is transferred to the sub- routine at address P:(R5) in program memory, and the contents of the R5 address regis- ter are then updated. Condition Codes: The condition codes are not affected by this instruction. A - 136 INSTRUCTION SET DETAILS MOTOROLA...
Page 406 1 0 1 r r r -(Rn) 1 1 1 r r r Absolute address 1 1 0 0 0 0 where “rrr” refers to an address register R0-R7 Timing: 4+jx oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 137...
Page 407 24-bit extension word. If the specified memory bit is not set, the program counter (PC) is incremented, and the extension word is ignored. However, the address register specified in the effective address field is always updated independently of the state of the A - 138 INSTRUCTION SET DETAILS MOTOROLA...
Page 408: Jsset
E — Not affected U — Not affected N — Not affected Z — Not affected V — Not affected C — Not affected For other source operands: The condition codes are not affected. MOTOROLA INSTRUCTION SET DETAILS A - 139...
Page 409 1 0 0 r r r 10111 (Rn+Nn) 1 0 1 r r r -(Rn) 1 1 1 r r r where “rrr” refers to an address register R0-R7 Timing: 6+jx oscillator clock cycles Memory: 2 program words A - 140 INSTRUCTION SET DETAILS MOTOROLA...
Page 410 Absolute Address in extension word Absolute Short Address aaaaaa Memory SpaceS Bit Number bbbbb 000000 X Memory 00000 • • Y Memory • 10111 111111 Timing: 6+jx oscillator clock cycles Memory: 2 program words MOTOROLA INSTRUCTION SET DETAILS A - 141...
Page 411 Absolute Address in extension word I/O Short Address pppppp Memory SpaceS Bit Number bbbbb 000000 X Memory 00000 • • Y Memory • 10111 111111 Timing: 6+jx oscillator clock cycles Memory: 2 program words A - 142 INSTRUCTION SET DETAILS MOTOROLA...
Page 412 4. The bit test is performed on the resulting 24-bit value, and the jump to sub- routine is taken if the bit tested is set. The original contents of A or B are not changed. Timing: 6+jx oscillator clock cycles Memory: 2 program words MOTOROLA INSTRUCTION SET DETAILS A - 143...
Page 413: Lsl
Explanation of Example: Prior to execution, the 56-bit B accumulator contains the value $00:F01234:13579B. The execution of the LSL B instruction shifts the 24-bit value in the B1 register one bit to the left and stores the result back in the B1 register. A - 144 INSTRUCTION SET DETAILS MOTOROLA...
Page 414 C — Set if bit 47 of A or B was set prior to instruction execution Instruction Format: LSL D Opcode: DATA BUS MOVE FIELD OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 145...
Page 415: Lsr
Explanation of Example: Prior to execution, the 56-bit A accumulator contains the value $37:444445:828180. The execution of the LSR A instruction shifts the 24-bit value in the A1 register one bit to the right and stores the result back in the A1 register. A - 146 INSTRUCTION SET DETAILS MOTOROLA...
Page 416 C — Set if bit 24 of A or B was set prior to instruction execution Instruction Format: LSR D Opcode: DATA BUS MOVE FIELD OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 147...
Page 417 R1 address register. Normally N0 would be added to R0 and deposited in R0. However, for an LUA instruction, the contents of both the R0 and N0 address registers are not affected. A - 148 INSTRUCTION SET DETAILS MOTOROLA...
Page 418 0 1 1 r r r where “rrr” refers to a source address register R0–R7 where “nnn” refers to a destination address register R0–R7 or N0–N7 Timing: 4 oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 149...
Page 419 $00:100000:000000 (0.125). The execution of the MAC X0,X0,A instruction squares the 24-bit signed value in the X0 register and adds the resulting 48-bit product to the 56-bit A ∗ accumulator (X0 X0+lA=0.145227144519197 approximately= $00:1296CD:9619C8=A). A - 150 INSTRUCTION SET DETAILS MOTOROLA...
Page 420 1 0 1 X1 Y0 1 1 0 Y1 X1 1 1 1 ∗ ∗ ∗ Note: Only the indicated S1 S2 combinations are valid. X1 X1 and Y1 Y1 are not valid. MOTOROLA INSTRUCTION SET DETAILS A - 151...
Page 421 3 places and filled with the sign bit (0 for a positive number and 1 for a neg- ative number) and then the result is added to the accumulator. Instruction Format 2: ± )S,#n,D Opcode 2: 16 15 Instruction Fields: Sign – A - 152 INSTRUCTION SET DETAILS MOTOROLA...
Page 422 16 10000 000000000000000010000000 17 10001 000000000000000001000000 18 10010 000000000000000000100000 19 10011 000000000000000000010000 20 10100 000000000000000000001000 21 10101 000000000000000000000100 22 10110 000000000000000000000010 23 10111 000000000000000000000001 Timing: 2 oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 153...
Page 423 Refer to the RND instruction for more complete information on the con- vergent rounding process. Example 1: ∗ MACR X0,Y0,B B,X0 Y:(R4)+N4,Y0 Y0+B B, and B, update X0,Y0,R4 Before Execution After Execution $123456 $100000 $123456 $987654 $00:100000:000000 $00:1296CE:000000 A - 154 INSTRUCTION SET DETAILS MOTOROLA...
Page 424 Note: The definitions of the E and U bits vary according to the scaling mode being used. Refer to Section A.5 for complete details. Instruction Format 1: ± MACR )S1,S2,D ± MACR )S2,S1,D Opcode 1: DATA BUS MOVE FIELD OPTIONAL EFFECTIVE ADDRESS EXTENSION MOTOROLA INSTRUCTION SET DETAILS A - 155...
Page 425 An alternate interpretation is that Y0 is negated, right shifted 10 places, filled with the sign bit (0 for a positive number and 1 for a negative number), the result is added to the accumulator and then rounded to a single precision number. A - 156 INSTRUCTION SET DETAILS MOTOROLA...
Page 426 16 10000 000000000000000010000000 17 10001 000000000000000001000000 18 10010 000000000000000000100000 19 10011 000000000000000000010000 20 10100 000000000000000000001000 21 10101 000000000000000000000100 22 10110 000000000000000000000010 23 10111 000000000000000000000001 Timing: 2 oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 157...
Page 427 A10 or B10 as the destination operand. Example: MOVE X0,A1 ;move X0 to A1 without sign ext. or zeroing Before Execution After Execution $234567 $234567 $FF:FFFFFF:FFFFFF $FF:234567:FFFFFF A - 158 INSTRUCTION SET DETAILS MOTOROLA...
Page 428 Instruction Format: MOVE Opcode: DATA BUS MOVE FIELD OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: See Parallel Move Descriptions for data bus move field encoding. Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 159...
Page 429 ALU operation and as a source for a parallel move operation, the parallel move operation occurs first and will use the data that exists in the accumulator before the execution of the data ALU operation has occurred. A - 160 INSTRUCTION SET DETAILS MOTOROLA...
Page 430 Note that the symbols used in decoding the various opcode fields of an instruction or par- allel move are completely arbitrary. Furthermore, the opcode symbols used in one instruction or parallel move are completely independent of the opcode symbols used in a different instruction or parallel move. MOTOROLA INSTRUCTION SET DETAILS A - 161...
Page 431 ;add X0 to A (no parallel move) Explanation of Example: This is an example of an instruction which allows parallel moves but does not have one. Condition Codes: The condition codes are affected by the instruction, not the move. A - 162 INSTRUCTION SET DETAILS MOTOROLA...
Page 432 INSTRUCTION DESCRIPTIONS No Parallel Data Move Instruction Format: ( ..) Opcode: 16 15 INSTRUCTION OPCODE Instruction Format: (defined by instruction) Timing: mv oscillator clock cycles Memory: mv program words MOTOROLA INSTRUCTION SET DETAILS A - 163...
Page 433 See the restrictions discussed in A.9.6 - R, N, and M Register Restric- tions on page A-310. A - 164 INSTRUCTION SET DETAILS MOTOROLA...
Page 434 8-bit immediate short operand into the eight LS bits of the R1 register and zeros the remaining eight MS bits of that register. The 8-bit value is interpreted as an unsigned integer since its destination is the R1 address register. MOTOROLA INSTRUCTION SET DETAILS A - 165...
Page 435 The condition codes are not affected by this type of parallel move. Instruction Format: ( ..) #xx,D Opcode: 16 15 INSTRUCTION OPCODE Instruction Fields: #xx=8-bit Immediate Short Data=iiiiiiii A - 166 INSTRUCTION SET DETAILS MOTOROLA...
Page 436 0 1 1 1 0 0 1 1 1 1 R0-R7 1 0 r N0-N7 1 1 n n n where “rrr”=Rn number where “nnn”=Nn number Timing: mv oscillator clock cycles Memory: mv program words MOTOROLA INSTRUCTION SET DETAILS A - 167...
Page 437 See the restrictions discussed in A.9.6 - R, N, and M Register Restric- tions on page A-310. A - 168 INSTRUCTION SET DETAILS MOTOROLA...
Page 438 $001234 and the 16-bit address offset register N5 contains the value $0000. The execu- tion of the parallel move portion of the instruction, Y1,N5, moves the 16 LS bits of the 24- bit value in the Y1 register into the 16-bit N5 register. MOTOROLA INSTRUCTION SET DETAILS A - 169...
Page 439 S — Computed according to the definition in A.5 CONDITION CODE COMPUTATION L — Set if data limiting has occurred during parallel move Instruction Format: ( ..) S,D Opcode: 16 15 INSTRUCTION OPCODE A - 170 INSTRUCTION SET DETAILS MOTOROLA...
Page 440 0 1 1 1 0 0 1 1 1 1 R0-R7 1 0 r N0-N7 1 1 n n n where “rrr”=Rn number where “nnn”=Nn number Timing: mv oscillator clock cycles Memory: mv program words MOTOROLA INSTRUCTION SET DETAILS A - 171...
Page 441 R3 register to the value in the N3 register and storing the 16-bit result back in the R3 address register. Condition Codes: The condition codes are not affected by this type of parallel move. A - 172 INSTRUCTION SET DETAILS MOTOROLA...
Page 442 0 1 r r r (Rn)- 1 0 r r r (Rn)+ 1 1 r r r where “rrr” refers to an address register R0-R7 Timing: mv oscillator clock cycles Memory: mv program words MOTOROLA INSTRUCTION SET DETAILS A - 173...
Page 443 24-bit destination register, the 16 LS bits of the destina- tion register are loaded with the contents of the 16-bit source operand, and the eight MS bits of the 24-bit destination register are zeroed. A - 174 INSTRUCTION SET DETAILS MOTOROLA...
Page 444 Note: The MOVE A,X:ea operation will result in a 24-bit positive or negative saturation constant being stored in the specified 24-bit X memory location if the signed integer por- tion of the A accumulator is in use. MOTOROLA INSTRUCTION SET DETAILS A - 175...
Page 445 1 0 0 r r r (Rn+Nn) 1 0 1 r r r -(Rn) 1 1 1 r r r Absolute address 1 1 0 0 0 0 Immediate data 1 1 0 1 0 0 A - 176 INSTRUCTION SET DETAILS MOTOROLA...
Page 446 0 1 1 1 0 0 1 1 1 1 R0-R7 1 0 r N0-N7 1 1 n n n where “rrr”=Rn number where “nnn”=Nn number Timing: mv oscillator clock cycles Memory: mv program words MOTOROLA INSTRUCTION SET DETAILS A - 177...
Page 447 Instruction Fields: aa=6-bit Absolute Short Address=aaaaaa Register W Absolute Short Address a a a a a a Read S 0 0 0 0 0 0 • Write D 1 1 1 1 1 1 A - 178 INSTRUCTION SET DETAILS MOTOROLA...
Page 448 0 1 1 1 0 0 1 1 1 1 R0-R7 1 0 r N0-N7 1 1 n n n where “rrr”=Rn number where “nnn”=Nn number Timing: mv oscillator clock cycles Memory: mv program words MOTOROLA INSTRUCTION SET DETAILS A - 179...
Page 449 B0, B1, B2, or B as its destination D1. That is, duplicate destinations are NOT allowed within the same instruction. A - 180 INSTRUCTION SET DETAILS MOTOROLA...
Page 450 A,X:$1234 A,Y0, moves the 24-bit limited positive saturation constant $7FFFFF into both the X:$1234 memory location and the Y0 register since the signed portion of the A accumulator was in use. MOTOROLA INSTRUCTION SET DETAILS A - 181...
Page 451 (B,X:(R1)+X0,B) moves the 24-bit limited value of B ($800000) into the X:$1234 memory location and the X0 register ($400000) into accumulator B1 ($400000), sign extends B1 into B2 ($00), and zero fills B0 ($000000). It also increments R1 to $1235. A - 182 INSTRUCTION SET DETAILS MOTOROLA...
Page 452 0 0 r r (Rn+Nn) 0 1 r r -(Rn) 1 1 r r Absolute address 1 0 0 0 0 Immediate data 1 0 1 0 0 where “rrr” refers to an address register R0–R7 MOTOROLA INSTRUCTION SET DETAILS A - 183...
Page 453 S/L Sign Ext Zero d S/L f Sign Ext Zero 0 0 no 0 yes 0 1 no 1 yes 1 0 yes 1 1 yes Timing: mv oscillator clock cycles Memory: mv program words A - 184 INSTRUCTION SET DETAILS MOTOROLA...
Page 454 1 1 1 r r r where “rrr” refers to an address register R0–R7 Sign Ext Zero MOVE Opcode A X:ea X0 A B X:ea X0 B Timing: mv oscillator clock cycles Memory: mv program words MOTOROLA INSTRUCTION SET DETAILS A - 185...
Page 455 24-bit destination register, the 16 LS bits of the destina- tion register are loaded with the contents of the 16-bit source operand, and the eight MS bits of the 24-bit destination register are zeroed. A - 186 INSTRUCTION SET DETAILS MOTOROLA...
Page 456 A2 portion of the accumulator, and zeros the lower 24-bit A0 portion of the accumulator. Condition Codes: S — Computed according to the definition in A.5 CONDITION CODE COMPUTATION L — Set if data limiting has occurred during parallel move. MOTOROLA INSTRUCTION SET DETAILS A - 187...
Page 457 0 0 r r (Rn+Nn) 0 1 r r -(Rn) 1 1 r r Absolute address 1 0 0 0 0 Immediate data 1 0 1 0 0 where “rrr” refers to an address register R0–R7 A - 188 INSTRUCTION SET DETAILS MOTOROLA...
Page 458 0 1 1 1 0 0 1 1 1 1 R0-R7 1 0 r N0-N7 1 1 n n n where “rrr”=Rn number where “nnn”=Nn number Timing: mv oscillator clock cycles Memory: mv program words MOTOROLA INSTRUCTION SET DETAILS A - 189...
Page 459 ( ..) S,Y:aa Opcode: 16 15 INSTRUCTION OPCODE Instruction Fields: aa=6-bit Absolute Short Address=aaaaaa Register W Absolute Short Address aaaaaa Read S 000000 • Write D 1 111111 A - 190 INSTRUCTION SET DETAILS MOTOROLA...
Page 460 0 1 1 1 0 0 1 1 1 1 R0-R7 1 0 r N0-N7 1 1 n n n where “rrr”=Rn number where “nnn”=Nn number Timing: mv oscillator clock cycles Memory: mv program words MOTOROLA INSTRUCTION SET DETAILS A - 191...
Page 461 B0, B1, B2, or B as its destination D2. That is, duplicate destinations are NOT allowed within the same instruction. A - 192 INSTRUCTION SET DETAILS MOTOROLA...
Page 462 (B0), and finally uses the contents of the 16-bit N6 address offset register to update the value in the 16-bit R6 address register. The contents of the N6 address offset register are not affected. MOTOROLA INSTRUCTION SET DETAILS A - 193...
Page 463 (Y0,B B,Y:(R1)+) moves the Y0 register ($600000) into accumulator B1 ($600000), sign extends B1 into B2 ($00), and zero fills B0 ($000000). It also moves the 24-bit lim- ited value of B ($7FFFFF) into the Y:$1234 memory location and increments R1 to $1235. A - 194 INSTRUCTION SET DETAILS MOTOROLA...
Page 464 ( ..) S1,D1 Y:ea,D2 ( ..) S1,D1 S2,Y:ea ( ..) S1,D1 #xxxxxx,D2 Opcode: INSTRUCTION OPCODE OPTIONAL EFFECTIVE ADDRESS EXTENSION MOTOROLA INSTRUCTION SET DETAILS A - 195...
Page 465 S2,D2 f f S/L Sign Ext Zero X0 0 0 0 no B 1 yes X1 1 0 1 no 1 0 yes 1 1 yes Timing: mv oscillator clock cycles Memory: mv program words A - 196 INSTRUCTION SET DETAILS MOTOROLA...
Page 466 1 1 1 r r r where “rrr” refers to an address register R0–R7 DEST DEST S, D Sign Ext Zero MOVE Opcode Y:ea Y:ea Timing: mv oscillator clock cycles Memory: mv program words MOTOROLA INSTRUCTION SET DETAILS A - 197...
Page 467 Note: The operands A10, B10, X, Y, AB, and BA may be used only for a 48-bit long memory move as previously described. These operands may not be used in any other type of instruction or parallel move. A - 198 INSTRUCTION SET DETAILS MOTOROLA...
Page 468 24-bit positive and/or negative saturation constant(s) being stored in the specified 24-bit X and/or Y memory location(s) if the signed integer portion of the A and/ or B accumulator(s) is in use. MOTOROLA INSTRUCTION SET DETAILS A - 199...
Page 469 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 A2,B2 A0,B0 1 1 0 B2,A2 B0,A0 1 1 1 Timing: mv oscillator clock cycles Memory: mv program words A - 200 INSTRUCTION SET DETAILS MOTOROLA...
Page 470 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 A2,B2 A0,B0 1 1 0 B2,A2 B0,A0 1 1 1 Timing: mv oscillator clock cycles Memory: mv program words MOTOROLA INSTRUCTION SET DETAILS A - 201...
Page 471 ALU operation. That is, duplicate sources are allowed within the same instruction. Note that S1 and S2 may specify the same register. A - 202 INSTRUCTION SET DETAILS MOTOROLA...
Page 472 16-bit N4 address offset register. The contents of the N4 address offset register are not affected. Condition Codes: S — Computed according to the definition in A.5 CONDITION CODE COMPUTATION L — Set if data limiting has occurred during parallel move. MOTOROLA INSTRUCTION SET DETAILS A - 203...
Page 473 M M R R R (Rn)+Nn 0 1 s s s (Rn)- 1 0 s s s (Rn)+ 1 1 s s s (Rn) 0 0 s s s where “sss” refers to an address register R0–R7 A - 204 INSTRUCTION SET DETAILS MOTOROLA...
Page 474 X effective address, previously described Register W S2, D2 f f S/L Sign Ext Zero Read S2 0 Write D2 1 1 0 yes 1 1 yes Timing: mv oscillator clock cycles Memory: mv program words MOTOROLA INSTRUCTION SET DETAILS A - 205...
Page 475 When a 56-bit accumulator (A or B) is specified as a source operand, the accumulator value is optionally shifted according to the scaling mode bits S0 and S1 in the system status register (SR). If the data out of the shifter indicates that the accumulator extension A - 206 INSTRUCTION SET DETAILS MOTOROLA...
Page 476 A MOVEC instruction used within a DO loop which specifies SSH as the source oper- and or LA, LC, SR, SP, SSH, or SSL as the destination operand cannot begin at the address LA – 2, LA – 1, or LA within that DO loop. MOTOROLA INSTRUCTION SET DETAILS A - 207...
Page 477 MOVEC LC,X0 instruction moves the contents of the 16-bit LC register into the 16 LS bits of the 24-bit X0 register and zeros the 8 MS bits of the X0 register. A - 208 INSTRUCTION SET DETAILS MOTOROLA...
Page 478 L — Set if data limiting has occurred during the move Instruction Format: MOVE(C) X:ea,D1 MOVE(C) S1,X:ea MOVE(C) Y:ea,D1 MOVE(C) S1,Y:ea MOVE(C) #xxxx,D1 Opcode: OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: ea=6-bit Effective Address=MMMRRR MOTOROLA INSTRUCTION SET DETAILS A - 209...
Page 479 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 where “nnn” = Mn number (M0–M7) Timing: 2+mvc oscillator clock cycles Memory: 1+ea program words A - 210 INSTRUCTION SET DETAILS MOTOROLA...
Page 480 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 where “nnn” = Mn number (M0–M7) Timing: 2+mvc oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 211...
Page 481 1 1 1 1 1 1 0 0 1 1 1 0 0 0 1 1 1 1 where “nnn” = Rn number (R0 - R7) Nn number (N0 - N7) Mn number (M0 - M7) A - 212 INSTRUCTION SET DETAILS MOTOROLA...
Page 482 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 where “nnn” = Mn number (M0–M7) Timing: 2+mvc oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 213...
Page 483 24 LS zeros. Whenever a 16-bit source operand S is to be moved into a 24-bit destination, the 16-bit source is loaded into the LS 16 bits of the destination operand, and the remaining 8 MS bits of the destination are zeroed. Note that for 24-bit source A - 214 INSTRUCTION SET DETAILS MOTOROLA...
Page 484 RTS instruction. A MOVEM instruction which specifies SP as the destination operand cannot be used immediately before a MOVEC, MOVEM, or MOVEP instruction which specifies SSH or SSL as the source operand. MOTOROLA INSTRUCTION SET DETAILS A - 215...
Page 485 C — Set according to bit 0 of the source operand ≠ For D SR operand: S — Computed according to the definition in A.5 CONDITION CODE COMPUTATION L — Set if data limiting has occurred during the move A - 216 INSTRUCTION SET DETAILS MOTOROLA...
Page 486 1 1 r r (Rn) 0 0 r r (Rn+Nn) 0 1 r r -(Rn) 1 1 r r Absolute address 1 0 0 0 0 where “rrr” refers to an address register R0–R7 MOTOROLA INSTRUCTION SET DETAILS A - 217...
Page 487 1 1 1 1 1 1 0 0 1 1 1 0 0 0 1 1 1 1 where “nnn” = Rn number (R0 - R7) Nn number (N0 - N7) Mn number (M0 - M7) A - 218 INSTRUCTION SET DETAILS MOTOROLA...
Page 488 0 0 1 1 1 1 where “nnn” = Rn number (R0 - R7) Nn number (N0 - N7) Mn number (M0 - M7) Timing: 6+ea+ap oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 219...
Page 489 P memory effective address. If the system stack register SSH is specified as a source operand, the system stack pointer (SP) is postdecremented by 1 after SSH has been read. If the system stack reg- A - 220 INSTRUCTION SET DETAILS MOTOROLA...
Page 490 A MOVEP instruction used within a DO loop which specifies SSH as the source oper- and or LA, LC, SR, SP, SSH, or SSL as the destination operand cannot begin at the address LA–2, LA–1, or LA within that DO loop. MOTOROLA INSTRUCTION SET DETAILS A - 221...
Page 491 #$1113,X:<<$FFFE instruction moves the value $1113 into the 16-bit bus control regis- ter X:$FFFE, resulting in one wait state for all external X, external Y, and external pro- gram memory accesses and three wait states for all external I/O accesses. A - 222 INSTRUCTION SET DETAILS MOTOROLA...
Page 492 C — Set according to bit 0 of the source operand ≠ For D SR operand: S — Computed according to the definition in A.5 CONDITION CODE COMPUTATION L — Set if data limiting has occurred during the move MOTOROLA INSTRUCTION SET DETAILS A - 223...
Page 493 Move Peripheral Data Instruction Format (X: or Y: Reference): MOVEP X:ea,X:pp MOVEP Y:ea,X:pp MOVEP #xxxxxx,X:pp MOVEP X:pp,X:ea MOVEP X:pp,Y:ea MOVEP X:ea,Y:pp MOVEP Y:ea,Y:pp MOVEP #xxxxxx,Y:pp MOVEP Y:pp,Y:ea MOVEP Y:pp,Y:ea Opcode: OPTIONAL EFFECTIVE ADDRESS EXTENSION A - 224 INSTRUCTION SET DETAILS MOTOROLA...
Page 494 1 1 0 0 0 0 Read Immediate data 1 1 0 1 0 0 Write where “rrr” refers to an address register R0–R7 Timing: 2+mvp oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 225...
Page 495 1 0 1 r r –(Rn) 1 1 1 r r Absolute address 1 1 0 0 0 0 where “rrr” refers to an address register R0–R7 Timing: 4+mvp oscillator clock cycles Memory: 1+ea program words A - 226 INSTRUCTION SET DETAILS MOTOROLA...
Page 496 0 0 1 1 1 1 where “nnn” = Rn number (R0 - R7) Nn number (N0 - N7) Mn number (M0 - M7) Timing: 4+mvp oscillator clock cycles Memory: 1+ea program words MOTOROLA INSTRUCTION SET DETAILS A - 227...
Page 497 All other Data ALU instructions are executed as NOP’s when the processor is in the Dou- ble Precision Multiply Mode. Example 1: ∗ MPY –X1,Y1,A #$543210,Y0 ;–(X1 A, update Y0 Before Execution After Execution $800000 $800000 $C00000 $C00000 $00:000000:000000 $FF:C00000:000000 A - 228 INSTRUCTION SET DETAILS MOTOROLA...
Page 498 Note: The definitions of the E and U bits vary according to the scaling mode being used. Refer to Section A.5 CONDITION CODE COMPUTATION for complete details. Instruction Format 1: MPY (±)S1,S2,D MPY (±)S2,S1,D Opcode 1: DATA BUS MOVE FIELD OPTIONAL EFFECTIVE ADDRESS EXTENSION MOTOROLA INSTRUCTION SET DETAILS A - 229...
Page 499 An alternate interpretation is that X1 is right shifted 9 places and filled with the sign bit (0 for a positive number and 1 for a neg- ative number) and then the result is placed in the accumulator. A - 230 INSTRUCTION SET DETAILS MOTOROLA...
Page 500 16 10000 000000000000000010000000 17 10001 000000000000000001000000 18 10010 000000000000000000100000 19 10011 000000000000000000010000 20 10100 000000000000000000001000 21 10101 000000000000000000000100 22 10110 000000000000000000000010 23 10111 000000000000000000000001 Timing: 2 oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 231...
Page 501 24-bit signed value in the Y0 register, negates the resulting 48-bit product, rounds the ∗ result into B1, and zeros B0 (–Y0 Y0=–0.625856790961748 approximately= $FF:AFE3EC:B76B7E, which is rounded to the value $FF:AFE3ED:000000= –0.625856757164002=B). A - 232 INSTRUCTION SET DETAILS MOTOROLA...
Page 502 Note: The definitions of the E and U bits vary according to the scaling mode being used. Refer to Section A.5 CONDITION CODE COMPUTATION for complete details. Instruction Format 1: MPYR ( ±) S1,S2,D MPYR ( ±) S2,S1,D Opcode 1: DATA BUS MOVE FIELD OPTIONAL EFFECTIVE ADDRESS EXTENSION MOTOROLA INSTRUCTION SET DETAILS A - 233...
Page 503 X1 is negated and placed in the accumulator, right shift ed 14 places, filled with the sign bit (0 for a positive number and 1 for a negative number) and then rounded to a single precision number. A - 234 INSTRUCTION SET DETAILS MOTOROLA...
Page 504 16 10000 000000000000000010000000 17 10001 000000000000000001000000 18 10010 000000000000000000100000 19 10011 000000000000000000010000 20 10100 000000000000000000001000 21 10101 000000000000000000000100 22 10110 000000000000000000000010 23 10111 000000000000000000000001 Timing: 2 oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 235...
Page 505 V — Set if overflow has occurred in A or B result Note: The definitions of the E and U bits vary according to the scaling mode being used. Refer to Section A.5 CONDITION CODE COMPUTATION for complete details. A - 236 INSTRUCTION SET DETAILS MOTOROLA...
Page 506 INSTRUCTION SET DESCRIPTIONS Negate Accumulator Instruction Format: NEG D Opcode: DATA BUS MOVE FIELD OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 237...
Page 507 Execution continues with the instruction following the NOP. Example: ;increment the program counter Explanation of Example: The NOP instruction increments the program counter and completes any pending pipeline actions. Condition Codes: The condition codes are not affected by this instruction. A - 238 INSTRUCTION SET DETAILS MOTOROLA...
Page 508 INSTRUCTION SET DESCRIPTIONS No Operation Instruction Format: Opcode: 16 15 Instruction Fields: None Timing: 2 oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 239...
Page 509 $00:000000:000001, and the 16-bit R3 address register contains the value $0000. The repetition of the NORM R3,A instruction normalizes the value in the 56-bit accumu- lator and stores the resulting number of shifts performed during that normalization pro- A - 240 INSTRUCTION SET DETAILS MOTOROLA...
Page 510 Refer to Section A.5 CONDITION CODE COMPUTATION for complete details. Instruction Format: NORM Rn,D Opcode: 16 15 Instruction Fields: R R R n n n where “nnn” = Rn number Timing: 2 oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 241...
Page 511 L — Set if data limiting has occurred during parallel move N — Set if bit 47 of A or B result is set Z — Set if bits 47-24 of A or B result are zero V — Always cleared A - 242 INSTRUCTION SET DETAILS MOTOROLA...
Page 512 INSTRUCTION SET DESCRIPTIONS Logical Complement Instruction Format: Opcode: DATA BUS MOVE FIELD OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 243...
Page 513 L — Set if data limiting has occurred during parallel move N — Set if bit 47 of A or B result is set Z — Set if bits 47-24 of A or B result are zero V — Always cleared A - 244 INSTRUCTION SET DETAILS MOTOROLA...
Page 514 INSTRUCTION SET DESCRIPTIONS Logical Inclusive OR Instruction Format: Opcode: DATA BUS MOVE FIELD OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 245...
Page 515 Z — Set if bit 2 of the immediate operand is set V — Set if bit 1 of the immediate operand is set C — Set if bit 0 of the immediate operand is set A - 246 INSTRUCTION SET DETAILS MOTOROLA...
Page 516 Opcode: 16 15 Instruction Fields: #xx=8-bit Immediate Short Data = i i i i i i i i CCR 0 1 OMR 1 0 Timing: 2 oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 247...
Page 517 The absolute short and the immediate short addressing modes may also be used. The four MS bits of the 12-bit immediate value are zeroed to form the 16-bit value that is to be loaded into the loop counter (LC). A - 248 INSTRUCTION SET DETAILS MOTOROLA...
Page 518 REP instruction. Example: REP X0 ;repeat (X0) times ;X1 ∗ Y1+A MAC X1,Y1,A X:(R1)+,X1 Y:(R4)+,Y1 A, update X1,Y1 Before Execution After Execution $000100 $000100 $0000 $0000 MOTOROLA INSTRUCTION SET DETAILS A - 249...
Page 519 S — Computed according to the definition. See Notes on page A-255. L — Set if data limiting occurred. See Notes on page A-255. For other source operands: The condition code bits are not affected. A - 250 INSTRUCTION SET DETAILS MOTOROLA...
Page 520 1 0 0 r r r (Rn+Nn) 1 0 1 r r r -(Rn) 1 1 1 r r r where “rrr” refers to an address register R0-R7 Timing: 4+mv oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 251...
Page 521 Opcode: 16 15 Instruction Fields: aa=6-bit Absolute Short Address=aaaaaa Absolute Short Address aaaaaa Memory Space s 000000 X Memory • Y Memory • 111111 Timing: 4+mv oscillator clock cycles Memory: 1 program word A - 252 INSTRUCTION SET DETAILS MOTOROLA...
Page 522 #xxx=12-bit Immediate Short Data = hhhh i i i i i i i i Immediate Short Data hhhh i i i i i i i i i 000000000000 • • 111111111111 Timing: 4+mv oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 253...
Page 523 (See Notes on page A-255) 0 0 1 1 1 1 yes (See Notes on page A-255) where “nnn” = Rn number (R0 - R7) Nn number (N0 - N7) Mn number (M0 - M7) A - 254 INSTRUCTION SET DETAILS MOTOROLA...
Page 524 If the system stack register SSH is specified as a source operand, the system stack pointer (SP) is postdecremented by 1 after SSH has been read. Timing: 4 oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 255...
Page 525 ;reset all on-chip peripherals and IPR Explanation of Example: The execution of the RESET instruction resets all on-chip peripherals and the interrupt priority register (IPR). Condition Codes: The condition codes are not affected by this instruction A - 256 INSTRUCTION SET DETAILS MOTOROLA...
Page 526 INSTRUCTION SET DESCRIPTIONS RESET RESET Reset On-Chip Peripheral Devices Instruction Format: RESET Opcode: 16 15 Instruction Fields: None Timing: 4 oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 257...
Page 527 LS bits of a value to produce a rounded result. The rounding constant depends on the scaling mode being used as previously shown. Unfortunately, when using a twos-complement data representation, this process introduces a positive bias in the statistical distribution of the roundoff error. A - 258 INSTRUCTION SET DETAILS MOTOROLA...
Page 528 A accumulator into the MSP portion of the A accumulator (A1), using convergent rounding, and then zeros the LSP portion of the A accumulator (A0). Note that Case II is the special case that distinguishes convergent rounding from standard or biased rounding. MOTOROLA INSTRUCTION SET DETAILS A - 259...
Page 529 V — Set if overflow has occurred in A or B result Note: The definitions of the E and U bits vary according to the scaling mode being used. Refer to Section A.5 CONDITION CODE COMPUTATION for complete details. A - 260 INSTRUCTION SET DETAILS MOTOROLA...
Page 530 INSTRUCTION SET DESCRIPTIONS Round Accumulator Instruction Format: Opcode: DATA BUS MOVE FIELD OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 261...
Page 531 A1 register one bit to the left, shifting bit 47 into the carry bit C, rotating the carry bit C into bit 24, and storing the result back in the A1 register. A - 262 INSTRUCTION SET DETAILS MOTOROLA...
Page 532 C — Set if bit 47 of A or B was set prior to instruction execution Instruction Format: ROL D Opcode: DATA BUS MOVE FIELD OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 263...
Page 533 B1 register one bit to the right, shifting bit 24 into the carry bit C, rotating the carry bit C into bit 47, and storing the result back in the B1 register. A - 264 INSTRUCTION SET DETAILS MOTOROLA...
Page 534 C — Set if bit 24 of A or B was set prior to instruction execution. Instruction Format: ROR D Opcode: DATA BUS MOVE FIELD OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 265...
Page 535 ;pull PC and SR from system stack Explanation of Example: The RTI instruction pulls the 16-bit program counter (PC) and the 16-bit status register (SR) from the system stack and updates the system stack pointer (SP). A - 266 INSTRUCTION SET DETAILS MOTOROLA...
Page 536 V — Set according to the value pulled from the stack C — Set according to the value pulled from the stack Instruction Format: Opcode: 16 15 Instruction Fields: None Timing: 4+rx oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 267...
Page 537 Explanation of Example: The RTS instruction pulls the 16-bit program counter (PC) from the system stack and updates the system stack pointer (SP). Condition Codes: The condition codes are not affected by this instruction. A - 268 INSTRUCTION SET DETAILS MOTOROLA...
Page 538 INSTRUCTION DESCRIPTIONS Return from Subroutine Instruction Format: Opcode: 16 15 Instruction Fields: None Timing: 4+rx oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 269...
Page 539 ;sub. LS words; get other MS word in B SBC YB A10,L:<$4 ;sub. MS words with carry; save LS dif. MOVE B10,L:<$5 ;save MS difference Before Execution After Execution $00:000000:000000 $00:800000:000000 $800000:000000 $800000:000000 $00:000000:000003 $00:000000:000001 $000000:000001 $000000:000001 A - 270 INSTRUCTION SET DETAILS MOTOROLA...
Page 540 SUB X,A instruction. The SBC Y,B instruction then produces the correct MS 56-bit result. The actual 96-bit result is stored in memory using the A10 and B10 operands (instead of A and B) because shifting and limiting is not desired. MOTOROLA INSTRUCTION SET DETAILS A - 271...
Page 541 C — Set if a carry (or borrow) occurs from bit 55 of A or B result Note: The definitions of the E and U bits vary according to the scaling mode being used. Refer to Section A.5 CONDITION CODE COMPUTATION for complete details. A - 272 INSTRUCTION SET DETAILS MOTOROLA...
Page 542 INSTRUCTION DESCRIPTIONS Subtract Long with Carry Instruction Format: Opcode: DATA BUS MOVE FIELD OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 273...
Page 543 17T. If the IRQA pin is asserted when the STOP instruction is executed, the clock will not be gated off, and the internal delay counter will be started. A - 274 INSTRUCTION SET DETAILS MOTOROLA...
Page 544 The condition codes are not affected by this instruction. Instruction Format: STOP Opcode: 16 15 Instruction Fields: None Timing: The STOP instruction disables the internal clock oscillator and internal distribu- tion of the external clock. Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 275...
Page 545 A or B (A0 or B0) by loading the 24-bit operand into X0 or Y0, forming a 48-bit word by loading X1 or Y1 with the sign extension of X0 or Y0, and executing a SUB X,A or SUB Y,A instruction. A - 276 INSTRUCTION SET DETAILS MOTOROLA...
Page 546 0 1 0 1 Y0,B 1 0 1 1 0 1 1 0 X1,A 1 1 0 0 0 1 1 1 X1,B 1 1 0 1 Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 277...
Page 547 $00:004000:000000, and the 56-bit B accumulator contains the value $00:005000:000000. The SUBL A,B instruction subtracts the value in the A accumulator from two times the value in the B accumulator and stores the 56-bit result in the B accu- mulator. A - 278 INSTRUCTION SET DETAILS MOTOROLA...
Page 548 Refer to Section A.5 CONDITION CODE COMPUTATION for complete details. Instruction Format: SUBL S,D Opcode: DATA BUS MOVE FIELD OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 279...
Page 549 $80:000000:2468AC, and the 56-bit B accumulator contains the value $00:000000:123456. The SUBR B,A instruction subtracts the value in the B accumulator from one-half the value in the A accumulator and stores the 56-bit result in the A accu- mulator. A - 280 INSTRUCTION SET DETAILS MOTOROLA...
Page 550 Refer to Section A.5 CONDITION CODE COMPUTATION for complete details. Instruction Format: SUBR S,D Opcode: DATA BUS MOVE FIELD OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 281...
Page 551 An SWI instruction cannot be used in a fast interrupt routine. An SWI instruction cannot be repeated using the REP instruction. Example: ;begin SWI exception processing Explanation of Example: The SWI instruction suspends normal instruction execution and initiates SWI exception processing. A - 282 INSTRUCTION SET DETAILS MOTOROLA...
Page 552 INSTRUCTION DESCRIPTIONS Software Interrupt Condition Codes: The condition codes are not affected by this instruction. Instruction Format: Opcode: 16 15 Instruction Fields: None Timing: 8 oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 283...
Page 553 When used after the CMP or CMPM instructions, the Tcc instruction can perform many useful functions such as a “maximum value,” “minimum value,” “maximum absolute value,” or “minimum absolute value” function. The desired value is stored in the destina- A - 284 INSTRUCTION SET DETAILS MOTOROLA...
Page 554 16-bit R1 address register if the specified condition is true. If the specified condition is not true, a NOP is executed. Condition Codes: The condition codes are not affected by this instruction. MOTOROLA INSTRUCTION SET DETAILS A - 285...
Page 555 1 1 1 0 Y0,B 1 0 1 1 0 1 1 1 1 1 1 1 Y1,A 1 1 1 0 Y1,B 1 1 1 1 Timing: 2 oscillator clock cycles Memory: 1 program word A - 286 INSTRUCTION SET DETAILS MOTOROLA...
Page 556 1 0 1 1 0 1 1 1 1 1 1 1 Y1,A 1 1 1 0 Y1,B 1 1 1 1 where “nnn’’=Rn number (R0–R7) Timing: 2 oscillator clock cycles Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 287...
Page 557 TFR instruction does use the data shifter/limiters. Thus, the value stored in the 24-bit X1 register (not shown) would have been limited in this example. This example illustrates a triple move instruction. A - 288 INSTRUCTION SET DETAILS MOTOROLA...
Page 558 1 1 0 1 Y0,A 1 0 1 0 Y0,B 1 0 1 1 Y1,A 1 1 1 0 Y1,B 1 1 1 1 Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 289...
Page 559 Z — Set if A or B result equals zero V — Always cleared Note: The definitions of the E and U bits vary according to the scaling mode being used. Refer to Section A.5 CONDITION CODE COMPUTATION for complete details. A - 290 INSTRUCTION SET DETAILS MOTOROLA...
Page 560 INSTRUCTION DESCRIPTIONS Test Accumulator Instruction Format: Opcode: DATA BUS MOVE FIELD OPTIONAL EFFECTIVE ADDRESS EXTENSION Instruction Fields: Timing: 2+mv oscillator clock cycles Memory: 1+mv program words MOTOROLA INSTRUCTION SET DETAILS A - 291...
Page 561 A WAIT instruction cannot be repeated using the REP instruction. Example: WAIT ;enter low power mode, wait for interrupt Explanation of Example: The WAIT instruction suspends normal instruction execution and waits for an unmasked interrupt or external RESET to occur. A - 292 INSTRUCTION SET DETAILS MOTOROLA...
Page 562 16 15 Instruction Fields: None Timing: The WAIT instruction takes a minimum of 16 cycles to execute when an internal interrupt is pending during the execution of the WAIT instruction Memory: 1 program word MOTOROLA INSTRUCTION SET DETAILS A - 293...
Page 563 APPENDIX B BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B - 1...
Page 564 SECTION CONTENTS SECTION B.1 INTRODUCTION ................3 SECTION B.2 BENCHMARK PROGRAMS ............3 B - 2 BENCHMARK PROGRAMS MOTOROLA...
Page 565: B.1 Introduction
Figure B-5 represents the Real FFT code for the DSP56002, based on the Glenn Bergland algorithm. The code for these and other programs is free and available through the Dr. BuB elec- tronic bulletin board. MOTOROLA BENCHMARK PROGRAMS B - 3...
Page 566: B-1 27-Mhz Benchmark Results For The Dsp56001R27
13255 256 Point M-to-M FFT 2.453 ms 6793 66240 1024 Point P-to-M FFT 92.56 µs 2499 64 Point P-to-M FFT 347.9 µs 2048 9394 256 Point P-to-M FFT 1.489 ms 7424 40144 1024 Point B - 4 BENCHMARK PROGRAMS MOTOROLA...
Page 567 BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B - 5...
Page 568: B-1 20-Tap Fir Filter Example
BENCHMARK PROGRAMS page 132,66,0,6 ;******************************************************** ;Motorola Austin DSP Operation June 30, 1988 ;******************************************************** ;DSP56000/1 ;20 - tap FIR ﬁlter ;File name: 1-56.asm ;********************************************************************************************************************* Maximum sample rate: 379.6 kHz at 20.5 MHz/500.0 kHz at 27.0 MHz Memory Size: Prog: 4+6 words; Data: 2x20 words Number of clock cycles: 54 (27 instruction cycles) Clock Frequency: 20.5 MHz/27.0 MHz...
Page 569 BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B - 7...
Page 570 ;********************************************************************************************************************** movep y:input,x: (r0) ;input sample in memory x:(r0)+,x0 y: (r4)+,y0 #n-1 x0,y0,a x:(r0)+,x0 y:(r4)+,y0 macr x0,x0,a (r0)- movep a,y:output ;output ﬁltered sample ;********************************************************************************************************************* Figure B-1 20-Tap FIR Filter Example (Sheet 2 of 2) B - 8 BENCHMARK PROGRAMS MOTOROLA...
Page 571 BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B - 9...
Page 572: B-2 Radix 2, In-Place, Decimation-In-Time Fft
BENCHMARK PROGRAMS ;This program originally available on the Motorola DSP bulletin board. ;It is provided under a DISCLAIMER OF WARRANTY available from ;Motorola DSP Operation, 6501 William Cannon Drive, Austin, TX, 78735 ;Radix-2, In-Place, Decimation-In-Time FFT (smallest code size). ;Last Update 30 Sep 86 Version 1.1...
Page 573 BENCHMARK PROGRAMS MOTOROLA BENCHMARK PROGRAMS B - 11...
Page 574: B-5 Real Input Fft Based On Glenn Bergland Algorithm
;multiply groups per pass by two b1,n0 move a1,n2 _end_pass endm Figure B-2 Radix 2, In-Place, Decimation-In-Time FFT (Sheet 2 of 2) Figure B-5 Real Input FFT Based on Glenn Bergland Algorithm (Sheet 1 of 8) B - 12 BENCHMARK PROGRAMS MOTOROLA...
Page 575 BENCHMARK PROGRAMS Figure B-5 Real Input FFT Based on Glenn Bergland Algorithm (Sheet 2 of 8) MOTOROLA BENCHMARK PROGRAMS B - 13...
Page 576 BENCHMARK PROGRAMS page 132,66,0,6 ;********************************************************** ;Motorola Austin DSP Operation June 30, 1988 *********************************************************** ;DSP56000/1 ;8-pole 4-multiply cascaded canonic IIR ﬁlter ;File name: 4-56.asm ;********************************************************************************************************************** Maximum sample rate: 410.0 kHz at 20.5 MHz/540.0 kHz at 27.0 MHz Memory Size: Prog: 6+10 words; Data: 4(2+4) words Number of clock cycles: 50 (25 instruction cycles) Clock Frequency: 20.5 MHz/27.0 MHz...
Page 577 BENCHMARK PROGRAMS Figure B-5 Real Input FFT Based on Glenn Bergland Algorithm (Sheet 4 of 8) MOTOROLA BENCHMARK PROGRAMS B - 15...
Page 578 +,y0 ;push w(n) to w(n-1),y0=bi1/2 x1,y0,a x:(r0) +,x0 y:(r4) +,y0 ;next iter:x0=w(n-2),y0=ai2/2 end_cell ;round result movep a,y:output ;output sample ;**************************************************************************************** Figure B-5 Real Input FFT Based on Glenn Bergland Algorithm (Sheet 5 of 8) B - 16 BENCHMARK PROGRAMS MOTOROLA...
Page 579 BENCHMARK PROGRAMS Figure B-5 Real Input FFT Based on Glenn Bergland Algorithm (Sheet 6 of 8) MOTOROLA BENCHMARK PROGRAMS B - 17...
Page 580 BENCHMARK PROGRAMS page 132,60,1,1 ;newlms2n.asm New Implementation of the delayed LMS on the DSP56000 Revision C ;Memory map: Initial X x(n) x(n-1) x(n-2) x(n-3) x(n-4) ;hx is an unused value to make the calculations faster. ntaps input $FFC0 output $FFC1...
Page 581 (imaginary output) points/2 (bergtable) ;------------------------------------------------------------------- rfft56bt ident 1,3 page 132,60 nomd,nomex,loc,nocex,mu include ‘bergsincos’ include ‘bergorder’ include ‘norm2berg’ include ‘rfft-56b’ Figure B-5 Real Input FFT Based on Glenn Bergland Algorithm (Sheet 8 of 8) MOTOROLA BENCHMARK PROGRAMS B - 19...
Page 582 - number of points (2 - 32768, power of 2) coef base address of sine/cosine table negative cosine value in X memory negative sine value in Y memory 3.141592654 freq 2.0*pi/@cvf(points) y:coef B - 20 BENCHMARK PROGRAMS MOTOROLA...
Page 583 ;r0=i move a,x:(r0+n0) ;k-> bergtable ;k=k*2 move a,y1 ;save A content _star move r4,a ;r4=# of points x0,a ;x0=j, if j< points, cont _loop move x0,r0 ;r0=i+i=j,b=i move y1,a ;recover A=k move x:(r0+n0),y0 ;y0=bergtabl[j] MOTOROLA BENCHMARK PROGRAMS B - 21...
Page 584 ;get value move a,x:(r2)+ b,y:(r6)+ ;write back data_temp endm ; Real-Valued FFT for MOTOROLA DSP56000/1/2 based on Glenn Bergland’s algorithm ; ______________________________ rifft macro points,binlogsz,idata,odata,twiddle,bergtable move #idata,r0 ;r0 = ptr to a move #points/4,n0 ;bﬂys in ea group, half at ea pass...
Page 585 ;B=a+c=a’, A=next a,PUT d’ move B,x:(r0)+ y:(r4),y0 ;y0=next c, PUT a’ FirstGroupInPass n2,end_group ;rest groups in this pass move r5,r0 ;r0 ptr to next group a move r0,r4 ;r4 ptr to next group c MOTOROLA BENCHMARK PROGRAMS B - 23...
Page 586 B,x:(r7) ;A=d-b=d’,PUT a’ to x move y:(r4)+,B ;B=d x0,B A,y:(r1) ;B=d+b=b’, A=next a,PUT d’ move x:(r0)+,A B,y:(r7) ;A=next a, PUT b’ move x:(r2)+,x0 y:(r4)+,B ;x0=Wi,B=next c n2,end_lastg ;rest groups in the last pass B - 24 BENCHMARK PROGRAMS MOTOROLA...
Page 587 ; Note that only DC to Nyquist frequency range is calculated by this algorithm ; After twiddle factors and bergtable are generated, you may overwrite 'bergorder', ; 'norm2berg' by 'rfft-56b' for saving P memory. Performance ;---------------------------------------------------------------- ; Real input data points Clock cycle 1686 3846 8656 19296 MOTOROLA BENCHMARK PROGRAMS B - 25...
Page 588 1024 49776 ;------------------------------------------------------------------ Memory (word) ;---------------------------------------------------------------- P memory X memory Y memory points/2+ (real input) points/2+ (imaginary input ) points/4+ (SIN table) points/4+ (COS table) points/2+ (real output) points/2 (imaginary output) points/2 (bergtable) ;---------------------------------------------------------------- B - 26 BENCHMARK PROGRAMS MOTOROLA...
Page 589 We welcome your comments and suggestions. They help us provide you with better prod- uct documentation. Please send your suggestions/corrections to the Fax number or Email address above or mail this completed form to: Motorola Inc. 6501 Wm. Cannon Drive West Austin, Texas 78735-8598 Attn: Digital Signal Processing Documentation 1.
Page 590 DSP56100 Family Manual Trouble Report 2. Did you find the manual clear and easy to use? Please comment on specific sections that you feel need improvement. 3. What sections of this manual do you consider most important/least important.
Page 591 Applications ......1-7 unnormalized (bit 4) ... . 5-10, A-17 MOTOROLA INDEX - 1...
Page 592 Global Data Bus (GDB) ....2-3 data buses ..... 2-3 INDEX - 2 MOTOROLA...
Page 593 Low Power Divider ..... .9-3 Interrupt Execution ..... 7-26 MOTOROLA INDEX - 3...
Page 594 PC ........5-5 PCAP .......9-10 INDEX - 4 MOTOROLA...
Page 595 (LA) ....2-6 loop counter (LC) ....2-6 MOTOROLA INDEX - 5...
Page 596 Saturation Arithmetic ....3-9 Tracing (DSP56000/56001 only) ...7-22 SBC .......A-270 Training .

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Motorola DSP56000 Manual

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Section 1

Section 2

Section 3

Section 4

Section 5

Section 6

Section 7

Section 8

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