Transaction Termination Interrupt Enable (Ttie) Bit 9; Transfer Complete Interrupt Enable (Tcie) Bit 12; Clear Transmitter (Clrt) Bit 14 - Motorola DSP56305 User Manual

6.5.2.6

Transaction Termination Interrupt Enable (TTIE) Bit 9

The TTIE bit is used to enable a DSP56300 core interrupt request when in the PCI mode
(HM=$1) and the HI32, as a PCI master, has executed a time-out termination, or a target
initiated disconnect or retry termination. If TTIE is cleared, transaction termination
interrupt requests are disabled. If TTIE is set, a transaction termination interrupt request
will be generated if a transaction was terminated due to a disconnect (TDIS is set in the
DPSR), retry (TRTY is set) or time-out (TO is set). This bit is used for non-fatal
transaction terminations (i. e., not an abort or priority error).
Hardware and software resets clear TTIE.
6.5.2.7

Transfer Complete Interrupt Enable (TCIE) Bit 12

The TCIE bit is used to enable a DSP56300 core interrupt request when in the PCI mode
(HM = $1) and the host data transfer complete (HDTC) status bit in the DSP PCI status
register (DPSR) is set. If TCIE is cleared, transfer complete interrupt requests are
disabled. If TCIE is set, a transfer complete interrupt request will be generated if HDTC
is set.
Hardware and software resets clear TCIE.
6.5.2.8

Clear Transmitter (CLRT) Bit 14

The CLRT bit is used to clear the HI32 master-to-host bus data path in the PCI mode
(HM = $1). This bit is used after a transaction is ended prematurely.When CLRT is set by
the DSP56300 core, the HI32 hardware clears the master DSP-to-host bus data path (i.e.
the DTXM-HRXM FIFO is forced empty) - thus setting the PCI Master Transmit Data
Request bit (MTRQ) in the DPSR, and then clears CLRT. CLRT cannot be written zero by
the DSP56300 core.
To assure operation, CLRT may be set by the DSP56300 core, only if
• MARQ is set in the DPSR (i.e. the DSP56300 core is not currently performing a
PCI transaction); and
• No DSP56300 core DMA channel is enabled to service HI32 master transmit data
DMA requests.
CLRT is ignored when the HI32 is not in the PCI mode (HM≠$1).
Hardware and software resets clear CLRT.
MOTOROLA DSP56305 User's Manual
HOST INTERFACE (HI32)
DSP SIDE Programming Model
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