Receiver Wakeup Enable (Rwu) Scr Bit 6; Wired-Or Mode Select (Woms) Scr Bit 7; Receiver Enable (Re) Scr Bit 8 - Motorola DSP56305 User Manual

8.3.1.5

Receiver Wakeup Enable (RWU) SCR Bit 6

When RWU is set and the SCI is in an Asynchronous mode, the wakeup function is
enabled — that is, the SCI is asleep, and can be awakened by the event defined by the
WAKE bit. In the Sleep state, all interrupts and all receive flags except IDLE are disabled.
When the receiver wakes up, RWU is cleared by the wakeup hardware. The programmer
can also clear the RWU bit to wake up the receiver.
RWU can be used by the programmer to ignore messages that are for other devices on a
multidrop serial network. Wakeup On Idle Line (WAKE is cleared) or Wakeup On
Address Bit (WAKE is set) must be chosen.
1. When WAKE is cleared and RWU is set, the receiver does not respond to data on
the data line until an idle line is detected.
2. When WAKE is set and RWU is set, the receiver does not respond to data on the
data line until a data frame with Bit 9 set is detected.
When the receiver wakes up, the RWU bit is cleared, and the first frame of data is
received. If interrupts are enabled, the CPU is interrupted and the interrupt routine
reads the message header to determine if the message is intended for this DSP.
1. If the message is for this DSP, the message is received, and RWU is set to wait for
the next message.
2. If the message is not for this DSP, the DSP immediately sets RWU. Setting RWU
causes the DSP to ignore the remainder of the message and wait for the next
message.
RWU is cleared by hardware and software reset. RWU is ignored in the Synchronous
mode.
8.3.1.6

Wired-OR Mode Select (WOMS) SCR Bit 7

When the WOMS bit is set, the SCI TXD driver is programmed to function as an
open-drain output and can be wired together with other TXD signals in an appropriate
bus configuration, such as a master-slave multidrop configuration. An external pullup
resistor is required on the bus. When the WOMS is cleared, the TXD signal uses an active
internal pullup. WOMS is cleared by hardware and software reset.
8.3.1.7

Receiver Enable (RE) SCR Bit 8

When RE is set, the receiver is enabled. When RE is cleared, the receiver is disabled, and
data transfer from the Receive Shift Register to the Receive Data Register (SRX) is
inhibited. If RE is cleared while a character is being received, the reception of the
character is completed before the receiver is disabled. RE does not inhibit RDRF or
receive interrupts. RE is cleared by hardware and software reset.
MOTOROLA DSP56305 User's Manual
Serial Communication Interface (SCI)
SCI Programming Model
8-11