Measurement Input Period (Mode 5) - Motorola DSP56305 User Manual

Timer/Event Counter
Timer Modes of Operation
timer clock received following the next valid transition occurring on the TIO input signal
and the count is resumed. If the TRM bit is cleared, the counter continues to be
incremented on each timer clock, accumulating measurement results.
This process is repeated until the timer is disabled (i.e., TE is cleared). If the counter
overflows, the TOF bit is set; if TOIE is set, an overflow interrupt is generated. The
counter contents can be read at any time by reading the TCR.
9.4.2.3

Measurement Input Period (Mode 5)

Bit Settings Mode Characteristics
TC3 TC2 TC1 TC0 Mode Name Kind TIO Clock
0 1 0 1 5 Input Period Measurement Input Internal
In this mode, the timer counts the period between the reception of signal edges of the
same polarity across the TIO signal.
Set the TE bit to clear the counter and enable the timer. The value the timer is to count is
loaded into the TLR. After the first appropriate transition (as determined by the INV bit)
occurs on the TIO input signal, the counter is loaded with the TLR value on the first
timer clock signal received from either the DSP56305 clock divided by two (CLK/2), or
the prescaler clock output. Each subsequent clock signal increments the counter.
On each following signal transition of the same polarity that occurs on TIO, the TCF bit
in the TCSR is set, and if the TCIE bit is set, a compare interrupt is generated. The
counter contents are loaded into the TCR. The TCR then contains the elapsed time
between two signal transitions on the TIO signal (that is, the distance between TIO
edges).
On the next timer clock signal, if the TRM bit is set, the counter is loaded with the TLR
value, and the count is resumed, but if the TRM bit is cleared, the counter continues
being incremented on each timer clock signal, accumulating measurement results.
This process is repeated until the timer is disabled (i.e., TE is cleared). If the counter
overflows, the TOF bit is set, and if the TOIE bit is set, an overflow interrupt is
generated. The counter contents can be read at any time by reading the TCR.
The value of the INV bit determines whether the period is measured between
consecutive low-to-high (0 to 1) transitions of TIO or between consecutive high-to-low (1
to 0) transitions of TIO. If INV is set, high-to-low signal transitions are selected. If INV is
cleared, low-to-high signal transitions are selected.
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