Motorola DSP56305 User Manual page 132

24-bit digital signal processor
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Core Configuration
Interrupt Sources and Priorities
Interrupt
Starting
Address
VBA:$3C
VBA:$3E
VBA:$40
VBA:$42
VBA:$44
VBA:$46
VBA:$48
VBA:$4A
VBA:$4C
VBA:$4E
VBA:$50
VBA:$52
VBA:$54
VBA:$56
VBA:$58
VBA:$5A
VBA:$5C
VBA:$5E
VBA:$60
VBA:$62
VBA:$64
VBA:$66
VBA:$68
VBA:$6A
VBA:$6C
VBA:$6E
VBA:$70
VBA:$72
VBA:$74
VBA:$76
VBA:$78
4-14
Interrupt
Priority
Level
Range
0–2
Reserved
0–2
Reserved
0–2
ESSI1 Receive Data
0–2
ESSI1 Receive Data With Exception Status
0–2
ESSI1 Receive last slot
0–2
ESSI1 Transmit Data
0–2
ESSI1 Transmit Data with Exception Status
0–2
ESSI1 Transmit last slot
0–2
Reserved
0–2
Reserved
0–2
SCI Receive Data
0–2
SCI Receive Data with Exception Status
0–2
SCI Transmit Data
0–2
SCI idle Line
0–2
SCI Timer
0–2
Reserved
0–2
Reserved
0–2
Reserved
0–2
Host PCI Transaction Termination
0–2
Host PCI Transaction Abort
0–2
Host PCI Parity Error
0–2
Host PCI Transfer Complete
0–2
Host PCI Master Receive Request
0–2
Host Slave Receive Request
0–2
Host PCI Master Transmit Request
0–2
Host Slave Transmit Request
0–2
Host PCI Master Address Request
0–2 / 3
Host Command / Host NMI (Default)
0–2
Reserved
0–2
Reserved
0–2
FCOP Data Input Buffer Empty
DSP56305 User's Manual
Interrupt Source
MOTOROLA

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