Essi Transmit Data Registers; Essi Time Slot Register (Tsr); Transmit Slot Mask Registers (Tsma, Tsmb) - Motorola DSP56305 User Manual

Enhanced Synchronous Serial Interface (ESSI)
ESSI Programming Model
7.4.7

ESSI Transmit Data Registers

ESSI0:TX02, TX01, TX00; ESSI1:TX12, TX11, TX10
TX2, TX1, and TX0 are 24-bit write-only registers. Data to be transmitted is written into
these registers and automatically transferred to the Transmit Shift Registers (see
Figure 7-19 and Figure 7-20). The data transmitted (8, 12, 16, or 24 bits) is aligned
according to the value of the ALC bit. When the ALC bit is cleared, the MSB is Bit 23.
When ALC is set, the MSB is Bit 15. If the transmit data register empty interrupt has been
enabled, the DSP is interrupted whenever a Transmit Data Register becomes empty.
Note: When writing data to a peripheral device there is a two core clock cycle
pipeline delay until any status bits affected by this operation are updated. If
the user reads any of those status bits within the next two cycles, the bit will
not reflect its current status. See the DSP56300 Family Manual, Appendix B,
Polling a Peripheral Device for Write for further details.
7.4.8

ESSI Time Slot Register (TSR)

TSR is effectively a write-only null data register that is used to prevent data reception in
the current receive time slot. For the purposes of timing, TSR is a write-only register that
behaves like an alternative Receive Data Register except that rather than receiving data,
the receive data signals of all the enabled receivers are in the high-impedance state for
the current time slot.
7.4.9

Transmit Slot Mask Registers (TSMA, TSMB)

The Transmit Slot Mask Registers are two 16-bit read/write registers. When the TSMA
or TSMB is read to the internal data bus, the register contents occupy the two low-order
bytes of the data bus, and the high-order byte is zero-filled. In Network mode, these
registers are used by the transmitter(s) to determine what action to take in the current
transmission slot. Depending on the setting of the bits, the transmitter(s) either tri-state
their data signal(s) or transmit a data word and generate a transmitter empty condition
(TDE = 1).
TSMA and TSMB (see Figure 7-19 and Figure 7-20) can be seen as a single 32-bit register,
TSM. Bit k in TSM (TSMk) is an enable/disable control bit for transmission in slot
number K. When TSMk is cleared, all the transmit data signals of the enabled
transmitters are tri-stated during transmit time slot number K. The data is still
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