Table 10-7 Breakpoint 0 Read/Write Select Table; Table 10-8 Breakpoint 0 Condition Select Table; Table 10-9 Breakpoint 1 Read/Write Select Table; Bits 4–5 - Motorola DSP56305 User Manual

Table 10-7 Breakpoint 0 Read/Write Select Table

RW01 RW00
0 0
0 1
1 0
1 1
10.5.6.3 Breakpoint 0 Condition Code Select (CC00–CC01) Bits 4–5
The Breakpoint 0 Condition Code Select bits (CC00–CC01) define the condition of the
comparison between the current Memory Address (OMAL0) and the Memory Limit
Register 0 (OMLR0). See Table 10-8 for the definition of the CC00–CC01 bits.
CC01 CC00
0 0
0 1
1 0
1 1
10.5.6.4 Breakpoint 1 Read/Write Select (RW10–RW11) Bits 6–7
The Breakpoint 1 Read/Write Select (RW10–RW11) bits control define memory
breakpoint 1 to occur when a memory address accesses is performed for read, write or
both. See Table 10-9 for the definition of the RW10–RW11 bits.

Table 10-9 Breakpoint 1 Read/Write Select Table

RW11 RW10
0 0
0 1
1 0
1 1
MOTOROLA
Breakpoint disabled
Breakpoint on write access
Breakpoint on read access
Breakpoint on read or write access

Table 10-8 Breakpoint 0 Condition Select Table

Breakpoint on not equal
Breakpoint on equal
Breakpoint on less than
Breakpoint on greater than
Breakpoint disabled
Breakpoint on write access
Breakpoint on read access
Breakpoint read or write access
DSP56305 User's Manual
On-Chip Emulation Module
OnCE Memory Breakpoint Logic
Description
Description
Description
10-13