Table of Contents
Advertisement
13.5.3.3
Decoding Enable (DECEN)—VCRA Bit 2
The Decoding Enable bit (DECEN), when set, enables the module to perform
convolutional decoding. All mode parameters specifying the type of coding must be set
prior to entering this mode (that is, the registers VCRA, VCRB, VTPA, and VTPB must
be written, and VCNT, VWES, and VTSR may need to be written, prior to this
operation). At the end of the decoding (i.e. after VCNT reaches zero and the flush
operation is completed), the DECEN bit is cleared by the internal logic. When the VCOP
is in continuous mode (CME is set), the flush operation does not take place, and DECEN
is not cleared by the internal logic. When DECEN is cleared, the decoding operation
halts and the register contents are preserved. The decoding operation is resumed if
DECEN is set again.
13.5.3.4
Encoding Enable (ENCEN)—VCRA Bit 3
The Encoding Enable bit (ENCEN), when set, enables the module to perform
convolutional encoding. All mode parameters specifying the type of the coding must be
set prior to entering this mode; that is, the registers VCRA, VCRB, VTPA, and VTPB
must be written, and VCNT may need to be written, prior to this operation. At the end of
the encoding (i.e. after VCNT reaches zero) the ENCEN bit is cleared by the internal
logic. When the VCOP is in continuous mode (CME is set), ENCEN is not cleared by the
internal logic. When ENCEN is cleared, the encoding operation halts and the register
contents are preserved. The encoding operation is resumed if ENCEN is set again.
13.5.3.5
Equalization Enable (EQEN)—VCRA Bit 4
The Equalization Enable bit (EQEN), when set, enables the module to perform channel
equalization. All mode parameters specifying the type of the equalization must be set
prior to entering this mode (that is, the registers VCRA and VCRB must be written, and
VCNT and VTSR may need to be written, prior to this operation). Equalization uses
S-parameters and V-parameters, therefore these values (contained in the SP RAM and
VP RAM respectively) must be written using the Memory Access Mode prior to starting
equalization. At the end of equalization (that is, after VCNT reaches zero and the flush
operation is complete), the EQEN bit is cleared by the internal logic. When the VCOP is
in continuous mode (CME is set), the flush operation does not take place, and EQEN is
not cleared by the internal logic. When EQEN is cleared, the equalization operation halts
and the register contents are preserved. The equalization operation is resumed if EQEN
is set again.
13.5.3.6
Flush Enable (FLEN)—VCRA Bit 5
The Flush Enable bit (FLEN), when set, enables the module to perform the flush
operation in order to complete the current operation prior to its normal ending (i.e.
before the counter reaches zero), forcing the module to extract survivor path bits
remaining in Trellis RAM. The path to be flushed is defined by the VTSR register. At the
end of the flush operation the FLEN bit is cleared by the internal logic.
MOTOROLA
DSP56305 User's Manual
VITERBI CO-PROCESSOR
Programming Model
13-19
Advertisement
Chapters
Table of Contents
