Motorola DSP56305 User Manual page 24

24-bit digital signal processor
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14.4.1
CCOP Data FIFO Register (CDFR) . . . . . . . . . . . . . . . . . . 14-8
14.4.2
CCOP Count Register (CCNT) . . . . . . . . . . . . . . . . . . . . . . 14-9
14.4.2.1
Input Counter (IC[7:0])-CCNT Bits 7-0 . . . . . . . . . . . . 14-9
14.4.2.2
Run Counter (RC[7:0])-CCNT Bits 15-8 . . . . . . . . . . . 14-9
14.4.2.3
Output Counter (OC[6:0])-CCNT Bits 22-16 . . . . . . . 14-10
14.4.2.4
Continuous Mode (CM)-CCNT Bit 23. . . . . . . . . . . . . 14-10
14.4.3
Step Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10
14.4.3.1
Step Function Select Register (CSFS) . . . . . . . . . . . . . 14-10
14.4.3.1.1
14.4.3.1.2
14.4.3.1.3
14.4.3.1.4
14.4.3.1.5
14.4.3.1.6
14.4.3.1.7
14.4.3.2
Step Function Table A (CSFTA). . . . . . . . . . . . . . . . . . 14-12
14.4.3.3
Step Function Table B (CSFTB). . . . . . . . . . . . . . . . . . 14-12
14.4.3.4
Input Enable bits (INE[3:0])-CSFTB Bits 19-16 . . . . . 14-13
14.4.3.5
Output Enable bits (OUTE[3:0])-CSFTB Bits 23-20 . 14-14
14.4.4
CCOP Control Status Register (CCSR) . . . . . . . . . . . . . . 14-14
14.4.4.1
Enable bit (CEN)-CCSR Bit 0. . . . . . . . . . . . . . . . . . . 14-15
14.4.4.2
Processing Enable bit (PREN)-CCSR Bit 1 . . . . . . . . 14-15
14.4.4.3
Operating Mode bits (OPM[1:0])-CCSR Bits 5-4. . . . 14-15
14.4.4.4
Left-Right Connection bit (LRC)-CCSR Bit 8 . . . . . . . 14-16
14.4.4.5
Halt On Zero Detect bit (HOZD)-CCSR Bit 9 . . . . . . . 14-16
14.4.4.6
Force Shift bit (FOSH)-CCSR Bit 10 . . . . . . . . . . . . . 14-17
14.4.4.7
Data In Interrupt Enable bit (DIIE)-CCSR Bit 12 . . . . 14-17
14.4.4.8
Data Out Interrupt Enable bit (DOIE)-CCSR Bit 13 . . 14-17
14.4.4.9
Cipher Done Interrupt Enable bit (CDIE)-
CCSR Bit 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17
14.4.4.10
Parity Coding Done Interrupt Enable bit (PDIE)-
'
CCSR Bit 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17
14.4.4.11
Input Buffer Empty bit (INBE)-CCSR Bit 19 . . . . . . . . 14-18
14.4.4.12
Input FIFO Empty bit (INFE)-CCSR Bit 20. . . . . . . . . 14-18
14.4.4.13
Output FIFO Not Empty bit (OFNE)-CCSR Bit 21 . . . 14-18
14.4.4.14
Cipher Done bit (CIDN)-CCSR Bit 22 . . . . . . . . . . . . 14-18
xxii
Select Bit A (SBA[4:0])-CSFS Bits 4-0 . . . . . . . . . 14-11
Select Register A (SRA[1:0])-CSFS Bits 6-5 . . . . 14-11
Select Bit B (SBB[4:0])-CSFS Bits 12-8 . . . . . . . . 14-11
Select Register B (SRB[1:0])-CSFS Bits 14-13 . . 14-11
Select Bit C (SBC[4:0])-CSFS Bits 20-16 . . . . . . . 14-12
Select Register C (SRC[1:0])-CSFS Bits 22-21 . . 14-12
Reserved Bits-CSFS Bits 7, 15, 23 . . . . . . . . . . . . 14-12
DSP56305 User's Manual
MOTOROLA

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