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13.3.1
Peripheral Module Bus (PMB) Interface
The Peripheral Module Bus (PMB) Interface block provides control and status registers,
buffers the internal bus, decodes addresses, and generates and controls handshake
signals required for DMA and interrupt operations. This block also generates interrupt
and DMA trigger signals whenever data transfer is required.
13.3.2
Flow Control
The Flow Control block controls the Viterbi algorithm operations for one update cycle –
called a stage in the trellis.
13.3.3
Branch Metric
The Branch Metric block calculates a pair of branch metrics for every execution cycle.
The branch metrics values are calculated differently depending on the operation mode.
Viterbi Parameters (VP), loaded in the VP RAM, are required for the branch metric
calculation and for equalization. The DSP56300 core calculates the VPs based upon the
channel impulse response. The VCOP makes use of the symmetrical property of VP
values (V(k)=–V(n–k)), by requiring only n/2 VP values for an n-state trellis calculation,
for instance VP
for a 16-state, and VP
0–7
When performing decoding, the branch metrics calculation is based on the input symbol
data, the tap vectors, and the trellis state number.
When calculating an ACS butterfly
metric block calculates one value and negates it prior to delivering it to the ACS block.
For every ACS butterfly there are two associated VP values.
When performing equalization, the calculation is based on demodulated symbol data
which is the output of a Matched Filter (MF). The MF value is stored in the VDR as a
16-bit value.
MOTOROLA
for a 32-state.
0–15
2
, the pair of branch metrics are opposites. The branch
DSP56305 User's Manual
VITERBI CO-PROCESSOR
Block Description
13-7
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