Output Counter (Oc[6:0])—Ccnt Bits 22–16; Continuous Mode (Cm)—Ccnt Bit 23; Step Function Registers; Step Function Select Register (Csfs) - Motorola DSP56305 User Manual

CYCLIC CODE CO-PROCESSOR
CCOP Programming Model
during this phase). After loading the input data into the CDFR, the user should load this
counter with the number of processing cycles desired. Starting with the cycle after the
input phase is completed, the Run Counter decrements itself each cycle until it reaches
zero. Each cycle the Run Counter is non-zero, the CFSRs perform a shift.
14.4.2.3 Output Counter (OC[6:0])—CCNT Bits 22–16
The Output Counter (OC[6:0]) specifies how many bits in the CFSRs are to be sent to the
CDFR as output (the range is 0 to 120). After loading the input data into the CDFR, the
user should load this counter with the number of valid bits to be shifted (one bit at a
time) into the CDFR as output. Starting with the cycle after the run phase is completed,
the Output Counter decrements itself each cycle until it reaches zero. Each cycle the
Output Counter is non-zero, the outputs from all four CFSRs are XORed together and
the resulting bit is shifted into the CDFR as output. The Stepping function is enabled
during the Output Counter operation. When the Output Counter reaches zero, the
CCOP generates an interrupt indicating to the DSP56300 core that it has finished
processing.
14.4.2.4 Continuous Mode (CM)—CCNT Bit 23
The Continuous Mode (CM) bit enables the CCOP to operate continuously. When CM is
cleared, the CCOP operates on input data blocks of length defined by the Input Counter,
then it passes to the run and output phases according to the Run Counter and Output
Counter respectively. When CM is set, the Input Counter, Run Counter and Output
Counters are ignored and the CFSRs operate in a continuous mode, i.e. upon receiving a
new data word, it is shifted into the enabled CFSRs. Only the input phase is activated
when CM is set, while the run and output phases are disabled. The continuous mode can
be used, for example, to calculate a CRC syndrome value of a large data block
transferred to CCOP via core or DMA.
14.4.3

Step Function Registers

The Step Function Registers perform the step functions, one register (CSFS) defining the
address to the Step Function Table, the other two (CSFTA and CSFTB) containing the
Step Function Table. The eight words in this table are written at initialization. Each of the
four output bits of the table controls one CFSR, and is interpreted as shift (one) or
no-shift (zero) by the CFSR. The stepping function starts operation after the Input
Counter reaches zero, and stops after the Output Counter reaches zero (i.e., it is enabled
when the Run Counter and Output Counter are active).
14.4.3.1

Step Function Select Register (CSFS)

The Step Function Select Register (CSFS) is a 24-bit read/write register used to select
three bits from anywhere in the CFSRs. These bits form the address to the 8 × 4-bit Step
Function Table. The register is composed of three bit-sized subregisters (lettered A, B,
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