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VITERBI CO-PROCESSOR
Performance Analysis
13.8
PERFORMANCE ANALYSIS
The following table summarizes maximal VCOP performance in various GSM channels.
Table 13-11 Performance of Various GSM Channels
Channel
Rate
Type
TCH / F9.6
1/2
TCH / F4.8
1/3
TCH / F2.4
1/6
TCH / FS
1/2
TCH / H4.8
1/2
TCH / H2.4
1/3
TCH / HS
1/3
Equalization
N/A
Equalization
N/A
Equalization
N/A
Note:
1.
Setup and reset time excluded.
The number of cycles required to decode one bit grows exponentially depending on the
constraint length.
The VCOP processing time for other codes can be estimated using the following
equations, where values are as shown in Table 13-12 :
Table 13-12 Variables for Calculating Processing Time
13-34
Constraint
Trellis
Length
States
5
16
5
16
5
16
5
16
5
16
5
16
7
64
16
32
64
Symbol
Number Meaning
S
P
DSP56305 User's Manual
Clock
Data Bits In
a Block
Cycles
(After
Block
Decode)
Transfer)
244
8,416
152
5,472
72
2,912
189
6,656
244
8,416
152
5,472
104
14,016
61
2,656
62
4,640
63
8,608
Trellis_States
Bits_to_Process
1
Time
At 80
1
(for
Mhz (For
Block
Transfer)
105.2 µs
68.4 µs
36.4 µs
83.2 µs
105.2 µs
68.4 µs
175.2 µs
33.2 µs
58.0 µs
107.6 µs
MOTOROLA
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