Table 14-8 Operations During Parity Coding Processing - Motorola DSP56305 User Manual

CYCLIC CODE CO-PROCESSOR
Programming Considerations
14.6.5 Parity Coding Processing
Parity Coding processing is enabled when the CCOP is programmed to operate in one of
the Parity Coding modes (i. e., if OPM1 = 1). The processing flow is identical in both
Parity Coding modes.
The only difference between the two is that when OPM[1:0] = 11, two CFSRs (CFSRA
and CFSRB) are concatenated together to form one big CFSR with up to 48 stages. The
unused CFSRs are disabled to reduce power consumption.
The Parity Coding mode using one CFSR (OPM[1:0] = 10) is used to calculate the Cyclic
Redundancy Code (CRC) syndrome with a generator polynomial of up to 24 stages
(maximum degree of 24). This mode is basically used for the calculation of the Frame
Check Sequence (FCS) of a data block prior to transmission, or for the calculation of the
CRC for error detection of a received data block. In this mode only the first CFSR
(CFSRA) is enabled for shifts. It is possible to implement Fire coding and decoding for
burst error correction using this mode if the generator polynomial is of degree of 24 or
less. However, in practice, fire codes use higher degree generator polynomials, and they
can be implemented using Parity Coding mode with two concatenated CFSRs (OPM[1:0]
= 11).
The Parity Coding mode using two concatenated CFSRs (OPM[1:0] = 11) is used to
calculate the Cyclic Redundancy Code (CRC) syndrome with a generator polynomial of
up to 48 stages (maximum degree of 48). In practice, this mode is used for Fire coding
and decoding of burst error correction. The Fire coding is identical to FCS calculation
with generator polynomial of degree up to 48. In Fire decoding, the CCOP implements a
pre-multiply calculation and a zero detect function, and upon completion it provides the
DSP programmer with useful data for computing the burst location and the burst error
correction sequence.
Table summarizes the operations being conducted at the input and run phases in every
(enabled) CFSR during a Parity Coding processing session.

Table 14-8 Operations During Parity Coding Processing

Input Phase Run Phase
Input Data Enabled if INEx in CSFTB set Disabled
Shifts Enabled Enabled
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