Table 11-1 Jtag Instructions - Motorola DSP56305 User Manual

JTAG Port
TAP Controller
B3 B2
0
0
0
0
0
0
0
0
1
1
1
1
The parallel output of the instruction register is reset to 0010 in the Test-Logic-Reset
controller state, which is equivalent to the IDCODE instruction.
During the Capture-IR controller state, the parallel inputs to the instruction shift register
are loaded with 01 in the Least Significant Bits as required by the standard. The two
Most Significant Bits are loaded with the values of the core status bits OS1 and OS0 from
the OnCE controller. See
status bits.
11-8

Table 11-1 JTAG Instructions

Code
B1 B0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 x x
1 0 x
1 1 0
1 1 1
Section 10, On-Chip Emulation Module
DSP56305 User's Manual
Instruction
EXTEST
SAMPLE/PRELOAD
IDCODE
CLAMP
HI-Z
RESERVED
ENABLE_ONCE
DEBUG_REQUEST
RESERVED
RESERVED
RESERVED
BYPASS
, for a description of the
MOTOROLA