Motorola DSP56305 User Manual page 197

In the PCI mode:
• In memory space read/write transactions, the HI32 occupies 16384 Dwords (see
Figure 6-2). The HTXR FIFO and HRXS FIFO can be accessed by the host at 16377
Dword locations. These FIFOs appear to the external host as 16377 Dwords of
read/write memory. Registers are accessed as 32-bit Dwords.
• HAD1 and HAD0 should be zero during the address phase of a transaction. The
HI32 will respond with a target-disconnect transaction termination with the first
data phase if HAD1-HAD0≠$0 during the address phase.
• In configuration space read/write transactions, the HI32 occupies 64 Dwords (see
Figure 6-3). The configuration registers are accessed as 32-bit Dwords, thus
HAD1 ad HAD0 must be zero during the address phase. The HI32 will ignore the
transaction if HAD1-HAD0≠$0 during the address phase of a configuration
transaction.
• In PCI host-to-DSP data transfers to the HI32 registers (HCTR, HSTR, HCVR and
all configuration space registers): disabled byte lanes (i.e. the corresponding byte
enable line is deasserted) are not written and the corresponding bytes do not
contain significant data.
• In HI32 to PCI agent data transfers, all four byte lanes are driven with data,
regardless of the value of the byte enables.
• In HCTR, HSTR, HCVR and configuration space register accesses: if all four byte
lanes are disabled the HI32 completes the data phase without affecting any flags
or data.
• In PCI DSP-to-host data transfers via the HRXS or HRXM, all four byte lanes are
driven with data, in accordance with FC1-FC0 or HRF1-HRF0 bits, regardless of
the value of the byte enable signals (HC3/HBE3-HC0/HBE0).
• In PCI host-to-DSP data transfers, data is written to the HTXR FIFO, in
accordance with FC1-FC0 or HTF1-HTF0 bits, regardless of the value of the byte
enable signals (HC3/HBE3-HC0/HBE0).
• The HI32 will not reach dead-lock due to illegal PCI events. Illegal PCI events
bring the HI32 Master and Target state machines to the IDLE state.
• As a PCI target the HI32 executes the PCI bus command as described in
Table 6-12:
MOTOROLA DSP56305 User's Manual
HOST INTERFACE (HI32)
HOST SIDE Programming Model
6-49