Receive Data Register Full (Rdrf) Ssr Bit 2; Idle Line Flag (Idle) Ssr Bit 3; Overrun Error Flag (Or) Ssr Bit 4 - Motorola DSP56305 User Manual

Register is written. TDRE is set by the hardware, software, SCI individual, and stop
reset.
In the Synchronous mode, when using the internal SCI clock, there is a delay of up to 5.5
serial clock cycles between the time that STX is written until TDRE is set, indicating the
data has been transferred from the STX to the Transmit Shift Register. There is a 2 to 4
serial clock cycle delay between writing STX and loading the Transmit Shift Register; in
addition, TDRE is set in the middle of transmitting the second bit. If the clock stops
when using an external serial transmit clock, the SCI transmitter stops. TDRE is not set
until the middle of the second bit transmitted after the external clock starts. Gating the
external clock off after the first bit has been transmitted delays TDRE indefinitely.
In the Asynchronous mode, the TDRE flag is not set immediately after a word is
transferred from the STX or STXA to the Transmit Shift Register nor when the word first
begins to be shifted out. TDRE is set 2 cycles of the 16
×
16 clock cycles into the transmission time of the first data bit.
8.3.2.3

Receive Data Register Full (RDRF) SSR Bit 2

The RDRF bit is set when a valid character is transferred to the SCI Receive Data Register
from the SCI Receive Shift Register (regardless of the error bits condition). RDRF is
cleared when the SCI Receive Data Register is read or by the hardware, software, SCI
individual, and stop resets.
8.3.2.4

Idle Line Flag (IDLE) SSR Bit 3

IDLE is set when ten (or eleven) consecutive 1s are received. IDLE is cleared by a
start-bit detection. The IDLE status bit represents the status of the receive line. The
transition of IDLE from 0 to 1 can cause an IDLE interrupt (ILIE). IDLE is cleared by the
hardware, software, SCI individual, and Stop resets.
8.3.2.5

Overrun Error Flag (OR) SSR Bit 4

The OR flag bit is set when a byte is ready to be transferred from the Receive Shift
Register to the Receive Data Register (SRX) that is already full (RDRF = 1). The Receive
Shift Register data is not transferred to the SRX. The OR flag indicates that character(s) in
the received data stream may have been lost. The only valid data is located in the SRX.
OR is cleared when the SCI status Register (SSR) is read, followed by a read of SRX. The
OR bit clears the FE and PE bits—that is, overrun error has higher priority than FE or PE.
OR is cleared by the hardware, software, SCI individual, and stop resets.
MOTOROLA DSP56305 User's Manual
Serial Communication Interface (SCI)
SCI Programming Model
×
clock after the start bit—that is, 2
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