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13.5.4
Viterbi Control Register B (VCRB)
The Viterbi Control Register B (VCRB) is a 16-bit read/write control register used by the
DSP56300 core to control the enabling of the interrupts generated by the module and the
operation modes of the module. The VCRB bits are described in the following
paragraphs. All VCRB bits are cleared after hardware and software reset.
15
14
13
OCIE DNIE DOIE BFIE
Reserved bit, Read as zero, should be written with zero for future compatibility
Reserved for internal use. Should be written with zero for proper operation.
13.5.4.1
Initial State Enable (ISE)—VCRB Bit 0
The Initial State Enable bit (ISE) controls the decoder starting path metric values. When
ISE is set, the state defined by the IS[5:0] bits in the VTSR is initialized to an initial value
19
of 2
, while the rest of the states are initialized to zero. When ISE is cleared, all trellis
states path metrics are initialized to zero.
13.5.4.2
Flush Control (FLC)—VCRB Bit 1
The Flush Control bit (FLC) controls the Flush Mode of operation by determining which
ending state to flush to, as defined in Table 13-4.
13.5.4.3
Continuous Mode Enable (CME)—VCRB Bit 3
The Continuous Mode Enable (CME) bit enables the VCOP to operate continuously.
When CME is cleared, the VCOP operates on data blocks of length defined in the VCNT
register. When CME is set, the VCNT contents are ignored and the VCOP operates
continuously upon receiving new data words. When CME is set, the flush operation
does not take place as part of the decoding and equalization process, and bits ENCEN,
MOTOROLA
12
11
10
9
Figure 13-10 Viterbi Control Register B (VCRB)
Table 13-4 Flush Modes
FLC
Flush operation flushes the path
0
with the maximal path metric value
1
defined by the End State (ES[5:0]) bits
DSP56305 User's Manual
8
7
6
5
DIIE
WEDE
VITERBI CO-PROCESSOR
Programming Model
4
3
2
1
0
CME
FLC
ISE
AA1319
13-21
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