Figure 2-1 Signals Identified By Functional Group - Motorola DSP56305 User Manual

Signal/Connection Descriptions
Signal Groupings
V
CCP
4
V
CCQ
6
V
CCA
4
V
CCD
2
V
CCN
6
V
CCH
2
V
CCS
GND
P
GND
1P
4
GND
Q
6
GND
A
4
GND
D
2
GND
N
6
GND
H
2
GND
S
EXTAL
XTAL
CLKOUT
PCAP
PINIT/NMI
24
A0–A23
24
D0–D23
AA0–AA3/
4
RAS0–RAS3
RD
WR
BS
TA
BR
BG
BB
BL
CAS
BCLK
BCLK
Notes: 1. The HI32 port supports PCI and non-PCI bus configurations. Twenty-four of these HI32 signals can
also be configured alternately as GPIO signals (PB0–PB23).
2. The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC0–PC5), Port D
GPIO signals (PD0–PD5), and Port E GPIO signals (PE0–PE2), respectively.
3. TIO0–TIO2 can be configured as GPIO signals.

Figure 2-1 Signals Identified by Functional Group

2-4
DSP56305
Power Inputs:
PLL
Internal Logic
Address Bus
Data Bus
Bus Control
HI32
ESSI/SCI/Timer
Grounds:
PLL
(HI32) Port
PLL
Internal Logic
Address Bus
Data Bus
Bus Control
HI32
ESSI/SCI/Timer
Extended Synchronous
Serial Interface Port
CLOCK
PLL
Synchronous Serial
Interface Port 1
Port A
External
Address Bus
External
Communications
Data Bus
Interface (SCI) Port
External
Bus
Control
DSP56305 User's Manual
MODA/IRQA
MODB/IRQB
Interrupt/
MODC/IRQC
Mode
MODD/IRQD
Control
RESET
PCI Bus
Host
52
See Figure 2-2 for a listing of the Host
Interface
Interface/Port B Signals
1
3
SC00–SC02
0
SCK0
2
(ESSI0)
SRD0
STD0
3
Extended
SC10–SC12
SCK1
SRD1
2
(ESSI1)
STD1
Serial
RXD
2
TXD
SCLK
TIO0
3
Timers TIO1
TIO2
TCK
TDI
TDO
JTAG/OnC
TMS
E Port
TRST
DE
Universal Port B
Bus GPIO
Port C GPIO
PC0–PC2
PC3
PC4
PC5
Port D GPIO
PD0–PD2
PD3
PD4
PD5
Port E GPIO
PE0
PE1
PE2
Timer GPIO
TIO0
TIO1
TIO2
AA0355
MOTOROLA