Motorola DSP56305 User Manual page 17

10.4.2 OnCE Decoder (ODEC). . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
10.4.3 OnCE Status and Control Register (OSCR) . . . . . . . . . . . . 10-8
10.4.3.1 Trace Mode Enable (TME) Bit 0 . . . . . . . . . . . . . . . . . . . 10-8
10.4.3.2 Interrupt Mode Enable (IME) Bit 1. . . . . . . . . . . . . . . . . . 10-8
10.4.3.3 Software Debug Occurrence (SWO) Bit 2. . . . . . . . . . . . 10-9
10.4.3.4 Memory Breakpoint Occurrence (MBO) Bit 3 . . . . . . . . . 10-9
10.4.3.5 Trace Occurrence (TO) Bit 4. . . . . . . . . . . . . . . . . . . . . . 10-9
10.4.3.6 Reserved OCSR Bit 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
10.4.3.7 Core Status (OS0, OS1) Bits 6-7 . . . . . . . . . . . . . . . . . . 10-9
10.4.3.8 Reserved Bits 8-23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
10.5 ONCE MEMORY BREAKPOINT LOGIC . . . . . . . . . . . . . . . . 10-10
10.5.1 OnCE Memory Address Latch (OMAL) . . . . . . . . . . . . . . . 10-11
10.5.2 OnCE Memory Limit Register 0 (OMLR0) . . . . . . . . . . . . . 10-11
10.5.3 OnCE Memory Address Comparator 0 (OMAC0) . . . . . . . 10-11
10.5.4 OnCE Memory Limit Register 1 (OMLR1) . . . . . . . . . . . . . 10-11
10.5.5 OnCE Memory Address Comparator 1 (OMAC1) . . . . . . . 10-11
10.5.6 OnCE Breakpoint Control Register (OBCR) . . . . . . . . . . . 10-12
10.5.6.1 Memory Breakpoint Select (MBS0-MBS1)
Bits 0-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
10.5.6.2 Breakpoint 0 Read/Write Select (RW00-RW01)
Bits 2-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
10.5.6.3 Breakpoint 0 Condition Code Select (CC00-CC01)
Bits 4-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
10.5.6.4 Breakpoint 1 Read/Write Select (RW10-RW11)
Bits 6-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13
10.5.6.5 Breakpoint 1 Condition Code Select (CC10-CC11)
Bits 8-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
10.5.6.6 Breakpoint 0 and 1 Event Select (BT0-BT1)
Bits10-11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14
10.5.6.7 OnCE Memory Breakpoint Counter (OMBC) . . . . . . . . 10-14
10.5.6.8 Reserved Bits 12-15 . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
10.6 ONCE TRACE LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15
10.7 METHODS OF ENTERING THE DEBUG MODE . . . . . . . . . 10-16
10.7.1 External Debug Request During RESET Assertion . . . . . . 10-16
10.7.2 External Debug Request During Normal Activity . . . . . . . . 10-16
10.7.3 Executing the JTAG DEBUG_REQUEST Instruction . . . . 10-17
MOTOROLA DSP56305 User's Manual xv