Host Vector (Hv6-Hv0) Bits 7-1; Host Non-Maskable Interrupt (Hnmi) Bit 15; Hcvr Reserved Bits 31-16, 14-8 - Motorola DSP56305 User Manual

HOST INTERFACE (HI32)
HOST SIDE Programming Model
6.6.3.2

Host Vector (HV6-HV0) Bits 7-1

The seven HV bits select the host command interrupt address. When the host command
interrupt is recognized by the DSP56300 core interrupt control logic, the starting address
of the interrupt executed is 2
The host processor can select any of the 128 possible interrupt routine starting addresses
in the DSP by writing the interrupt routine starting address divided by two into HV.
This means that the host processor can force any of the existing interrupt routines (SSI,
Timer, IRQA, IRQB, etc.) and can use any of the reserved or otherwise unused starting
addresses provided they have been pre-programmed in the DSP. Non-maskable
interrupts of DSP56300 core can be forced by the host processor by setting the host
non-maskable interrupt (HNMI) bit in the HCVR. When HNMI set is recognized by the
HI32 command interrupt logic, the host command interrupt is processed with the
highest priority regardless of the current HI32 interrupt priority (as written in the
DSP56300 core peripheral priority register (IPRP)).
MV6-HV0 should not be used with a value of zero - the reset location, as this
location is normally programmed with a JMP instruction. Doing so will
cause an improper short interrupt.
The personal hardware reset sets HV to the default host command vector, which is via
programmable (see Section 6.10).
6.6.3.3

Host Non-Maskable Interrupt (HNMI) Bit 15

The HNMI bit is used by the host processor to force the generation of the host command
as non-maskable interrupt request. If HNMI and HC are set, the host command interrupt
is processed with the highest priority regardless of the current HI32 interrupt priority (as
written in the DSP56300 core peripheral priority register (IPRP)). If HNMI is cleared and
HC is set, the host command interrupt is processed in accordance with the priority
programmed in the IPRP register, and can be disabled by clearing HCIE in the DCTR.
The personal hardware reset clears HNMI.
6.6.3.4

HCVR Reserved Bits 31-16, 14-8

These unused bits are reserved for future expansion and should be written with zeros
for upward compatibility. They are read by the host processor as zeros.
6-74
×
(HV6-HV0).
CAUTION
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