9.2.5
Timer Prescaler Count Register (TPCR)
The Timer Prescaler Count Register (TPCR) is a 24-bit read-only register that reflects the
current value in the prescaler counter. The register bits are described below in Figure 9-4.
23
22
21
11
10
9
PC11
PC10
PC9
— reserved, read as 0, should be written with 0 for future compatibility
Figure 9-4 Timer Prescaler Count Register (TPCR)
9.2.5.1
Prescaler Counter Value PC[20:0] — TPCR Bits 20-0
These 21 bits contain the current value of the prescaler counter.
9.2.5.2
Reserved Bits — TPCR Bits 23-21
These reserved bits are read as 0 and should be written with 0 for future compatibility.
9.3
TIMER ARCHITECTURE
The DSP56305 views each timer as a memory-mapped peripheral with four registers
occupying four 24-bit words in the X data memory space. Either standard polled or
interrupt programming techniques can be used to service the timers. The three timers
are identical in functionality. Figure 9-5 shows the block diagram for a generic timer.
Figure 9-6 shows the programming model for a generic timer.
Each timer can use internal or external clocking and can interrupt the processor after a
number of events (clocks) specified by a user program, or signal an external device after
counting internal events. Each timer can also be used to trigger DMA transfers after a
specified number of events (clocks) has occurred. Each timer may use the prescaler clock
as its clock source.
Each timer uses one bidirectional signal as a timer signal (or GPIO signal, when not used
as a timer signal), called TIO0–2 for timers 0–2 respectively. Note the name is the same,
whether the signal is used for the timer or for GPIO.
MOTOROLA
20
19
18
PC20
PC19
PC18
8
7
6
PC8
PC7
PC6
DSP56305 User's Manual
17
16
15
PC17
PC16
PC15
5
4
3
PC5
PC4
PC3
Timer/Event Counter
Timer Architecture
14
13
12
PC14
PC13
PC12
2
1
0
PC2
PC1
PC0
9-7