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6.5.3.2
DSP PCI Data Burst Length (BL5-BL0) Bits 21-16
The BL5-BL0 bits control the PCI data burst length, the value of the BL5-BL0 bits being
the desired number of accesses in the burst, minus one. When the DPAR is written by the
DSP56300 core, while in the PCI mode (HM=$1), the master access counter is initialized
with the value of BL5-BL0. The burst length may be programmed from 1 (BL = $00) to 64
(BL = $3F) accesses.
If the master access counter is enabled (MACE = 1 in the DPCR) and the HI32 is the
active PCI master, the value of the counter is decremented after each data cycle in which
data is transferred (i.e. a data phase), until a value of $00 is reached. When the counter
value reaches $00, the HI32 PCI master will execute one more data phase and terminate
the transaction. A transaction may be terminated before the counter reaches $00 (e.g. a
target initiated transaction termination, or the bus grant was taken, or the DSP56300 core
wrote one to MTT). Note that the burst length (BL) is not changed. The value of the
counter at the end of a transaction is indicated by the RDC5-RDC0 bits in the DSP PCI
status register (DPSR).
Hardware and software resets clear BL5-BL0.
6.5.3.3
DSP Data Transfer Format Control (FC1-FC0) Bits 23 and 22
The FC1-FC0 bits define data transfer formats between the HI32 and a PCI agent when in
the PCI mode (HM=$1) and the HI32 is a bus master. The data transfer format converter
(see Figure ) operates according to the specified FC1-FC0 (see Table 6-5).
Table 6-8 HI32 (PCI Master) Data Transfer Formats
DSP to PCI Host Data Transfer
FC1
FC0
0
0
The two least significant bytes of two HRXM locations
are output.
HI32
MOTOROLA
Format
GDB/MDDB
X
DTXM
X
HRXM
X
HDTFC
PCI bus
DSP56305 User's Manual
HOST INTERFACE (HI32)
DSP SIDE Programming Model
PCI Host to DSP Data Transfer
Format
All 32 PCI data bits are written to the HTXR as two
zero-extended 16-bit words.
HI32
$0
$0
GDB/MDDB
DRXR
HTXR
HDTFC
PCI bus
6-29
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