Motorola DSP56305 User Manual page 72

Signal/Connection Descriptions
External Memory Expansion Port (Port A)
Table 2-8 External Bus Control Signals (Continued)
Signal
Type
Name
BB Input/
Output
BL Output
CAS Output
2-14
State During
Reset, Wait,
or Stop
Input Bus Busy—BB indicates that the bus is active. BB must
be asserted and deasserted synchronous to CLKOUT.
Only after BB is deasserted can the pending bus
master become the bus master (and then assert the
signal again). The bus master may keep BB asserted
after ceasing bus activity regardless of whether BR is
asserted or deasserted. This is called "bus parking"
and allows the current bus master to reuse the bus
without re-arbitration until another device requires
the bus. The deassertion of BB is done by an "active
pull-up" method (i.e., BB is driven high and then
released and held high by an external pull-up resistor).
BB requires an external pull-up resistor.
Driven High Bus Lock—BL is asserted at the start of an external
(Deasserted) divisible Read-Modify-Write (RMW) bus cycle,
remains asserted between the read and write cycles,
and is deasserted at the end of the write bus cycle. This
provides an "early bus start" signal for the bus
controller. BL may be used to "resource lock" an
external multi-port memory for secure semaphore
updates. Early deassertion provides an "early bus
end" signal useful for external bus control. If the
external bus is not used during an instruction cycle, BL
remains deasserted until the next external indivisible
RMW cycle. The only instructions that assert BL
automatically are the BSET, CLR, and BCHG
instructions when they are used to modify external
memory. An operation can also assert BL by setting
the BLH bit in the Bus Control Register.
Tri-stated Column Address Strobe—When the DSP is the bus
master, CAS is used by DRAM to strobe the column
address. Otherwise, if the Bus Mastership Enable
(BME) bit in the DRAM Control Register is cleared, the
signal is tri-stated.
DSP56305 User's Manual
Signal Description
MOTOROLA