Figure 7-9 Essi Clock Generator Functional Block Diagram - Motorola DSP56309 User Manual

Enhanced Synchronous Serial Interface (ESSI)
ESSI Programming Model
Note: The combination PSR = 1 and PM[7:0] = $00 (dividing F
synchronization problems and should not be used.
CRB(TE1)
SCn0
Sync:
TX #1, or
Flag0
CRB(SCD0)
Async:
RX clk
SCKn
Sync:
TX/RX clk
Async:
CRB(SCKD)
TX clk
/2
F
CORE

Figure 7-9 ESSI Clock Generator Functional Block Diagram

7.4.1.4 CRA Frame Rate Divider Control DC[4:0] Bits 16Ð12
The values of the DC[4:0] bits control the divide ratio for the programmable frame rate
dividers used to generate the frame clocks. In network mode, this ratio can be
interpreted as the number of words per frame minus one. In normal mode, this ratio
determines the word transfer rate.
The divide ratio can range from 1 to 32 (DC = 00000 to 11111) for normal mode and 2 to
32 (DC = 00001 to 11111) for network mode. A divide ratio of one (DC = 00000) in
network mode is a special case known as on-demand mode. In normal mode, a divide
ratio of one (DC = 00000) provides continuous periodic data word transfers. A bit-length
frame sync must be used in this case and is selected by setting the FSL[1:0] bits in the
CRA to (01). Both the hardware RESET signal and the software RESET instruction clear
DC[4:0].
The ESSI frame sync generator functional diagram is shown in Figure 7-10.
7-12
TX #1 or Flag0 Out Flag0 In
CRB(OF0) SSISR(IF0)
(Sync Mode) (Sync Mode)
CRB(SYN) = 1
SYN = 0 SCD0 = 1
Internal Bit Clock
CRA(PSR)
CRA(PM7:0)
/1 or /8 /1 to /256
1 0 0
(Opposite
from SSI)
DSP56309UM/D
SCD0 = 0
SYN = 0
RX Shift Register
RCLOCK
SYN = 1
TCLOCK
/8, /12, /16, /24, /32
Note: 1. F
CORE
clock frequency.
2. ESSI internal clock range:
min = F
max = F
255
3. ÔnÕ in signal name is ESSI # (0 or 1)
by 2) can cause
core
CRA(WL2:0)
/8, /12, /16, /24, /32
0 1 2 3 4,5
CRA(WL2:0)
0 1 2 3 4,5
TX Shift Register
is the DSP56300 Core internal
/4096
OSC
/4
OSC
MOTOROLA
RX
Word
Clock
TX
Word
Clock
AA0679