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VITERBI CO-PROCESSOR
Programming Model
13.5.3
Viterbi Control Register A (VCRA)
The Viterbi Control Register A (VCRA) is a 16-bit read/write control register used by the
DSP56300 core to control the main operation modes of the module. The VCRA bits are
described in the following paragraphs. All the VCRA bits are cleared after Hardware
and Software Reset.
15
14
13
12
CNST1 CNST0
Reserved bit, Read as zero, should be written with zero for future compatibility
When the five enable bits (MAEN, DECEN, ENCEN, EQEN, and FLEN) are cleared, the
module is in the idle state. In this mode, the module is inactive but the register contents
are preserved and they can be read or written by the DSP56300 core.
Only one of MAEN, DECEN, ENCEN, and EQEN may be set at a time. Setting more than
one of these bits is an illegal condition and will cause the VCOP operation to be
unpredictable.
13.5.3.1
Module Enable (ME)—VCRA Bit 0
The Module Enable bit (ME), when set, enables the operation of the VCOP. When ME is
cleared, the operation is disabled and the VCOP is in the VCOP individual reset state.
While in the VCOP individual reset state, internal logic and status bits are reset to the
same state produced by hardware or software reset. Control bits are not affected when
ME is cleared. ME is cleared by hardware or software reset.
13.5.3.2
Memory Access Enable (MAEN)—VCRA Bit 1
The Memory Access Mode enable bit (MAEN), when set, enables the core to access the
data of the internal RAMs. The VBER contains the address of the memory access while
VMEM contains the data. This mode is used when setting the SP and VP values for
channel equalization. After setting these parameters, the MAEN bit must be cleared by
the DSP56300 core.
13-18
11
10
9
RATE1 RATE0
Figure 13-9 Viterbi Control Register A (VCRA)
DSP56305 User's Manual
8
7
6
5
FLEN EQEN ENCEN DECEN MAEN
4
3
2
1
AA1318
MOTOROLA
0
ME
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