Bits 31-20, 18-17, 13, 10, And 0 - Motorola DSP56305 User Manual

• the HI32 as the selected target in a read transaction from the HRXS, will generate
a target initiated transaction termination (disconnect-C) if the HRXS is empty
(HRRQ = 0).
• the HI32 as the selected target in a write transaction to the HTXR, will generate a
target initiated transaction termination (disconnect-C) if the HTXR is full (HTXR
= 0).
• the HI32 as the selected target in a write transaction to the HCVR, will generate a
target initiated transaction termination (disconnect-C) if a host command is
pending (HC = 1).
TWSD is ignored when the HI32 is not in the PCI mode (HM≠$1).
The personal hardware reset clears TWSD.
6.6.1.10 HCTR Reserved Control Bits 31-20, 18-17, 13, 10, and 0
These bits are reserved for future expansion, they are read as zeros and should be
written with zeros for upward compatibility.
MOTOROLA DSP56305 User's Manual
HOST INTERFACE (HI32)
HOST SIDE Programming Model
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