Dsp56305 Block Diagram; Figure 1-1 Dsp56305 Block Diagram - Motorola DSP56305 User Manual

DSP56305 Overview

DSP56305 Block Diagram

With the exception of the Program Data Bus (PDB), all internal buses on the DSP56300
family members are 16-bit buses. The PDB is a 24-bit bus. Figure 1-1 provides a block
diagram of the DSP56305.
1.8 DSP56305 BLOCK DIAGRAM
51 6 6
Host
ESSI
Timer
Inter-
Inter-
face
face
HI32
Address
Generation
Unit
Six Channel
DMA Unit
Bootstrap
ROM
Internal
Data
Bus
Switch
Clock
Gen-
PLL
erator
Controller
EXTAL
2
XTAL
RESET
PINIT/NMI
Note: Memory sizes in the block diagram are default sizes, except for the I-Cache,
which is disabled by default. See
details about memory size.
1-14
3
SCI
Inter-
FCOP VCOP CCOP
face
Peripheral
Expansion Area
Program Program
Interrupt Decode
Controller
MODD/IRQA
MODC/IRQB
MODB/IRQC
MODA/IRQD

Figure 1-1 DSP56305 Block Diagram

DSP56305 User's Manual
Memory Expansion Area
P Memory X Memory
RAM RAM
6.5 K × 24 3.75 K × 24
(I-Cache
1 K × 24)
ROM
6 K × 24
YAB
XAB
PAB
DAB
24-Bit
DSP56300
Core
DDB
YDB
XDB
PDB
GDB
Data ALU
24 × 24 + 56 → 56-bit MAC
Program
Address
Two 56-bit Accumulators
Generator
56-bit Barrel Shifter
(On-Chip Memories) for more
Section 1.6.6
X Memory
RAM
2 K × 24
ROM
3 K × 24
External
24
Address
Bus
Address
Switch
External
Bus
15
Interface
and
I-Cache
Control
Control
External
24
Data
Bus
Data
Switch
Power
Mngmnt.
5
JTAG
OnCE™
DE
AA1366
MOTOROLA