Host Interrupt Request Handshake Mode(Hirh) Bit 18; Host Interrupt Request Drive Control (Hird) Bit 19 - Motorola DSP56305 User Manual

HOST INTERFACE (HI32)
DSP SIDE Programming Model
6.5.1.11

Host Interrupt Request Handshake Mode(HIRH) Bit 18

The HIRH bit controls the handshake mode of the HIRQ signal when the HI32 is in a
Universal Bus mode (HM = $2 or $3). HIRQ is asserted by the HI32 when a host
interrupt request (receive and/or transmit) is generated in the HI32. With HIRH cleared,
when a host interrupt request is generated, HIRQ is asserted for the number of
DSP56300 core clock cycles specified by the LT7-LT0 bits in the CLAT and then
deasserted. The duration of the HIRQ pulse is given by the following equation:
HIRQ_PULSE_WIDTH = (LT[7:0]_Value + 1) • DSP56300_Core_clock_cycle
If HIRH is set: HIRQ is deasserted when the interrupt request source is cleared (by the
corresponding host data access), masked (by TREQ = 0 or RREQ = 0) or disabled by the
DMA enable bit (DMAE) in the HCTR.
The value of HIRH may be changed only when HACT = 0.
HIRH is ignored when not in a Universal Bus mode (HM ≠ $2 or $3).
Hardware and software resets clear HIRH.
6.5.1.12

Host Interrupt Request Drive Control (HIRD) Bit 19

The HIRD bit controls the output drive of HIRQ signal when the HI32 is in a Universal
Bus mode (HM = $2 or $3). With HIRD cleared, the HIRQ signal is an open drain output
(i.e. driven low when asserted, released (high impedance) when deasserted). With HIRD
set, the HIRQ signal is always driven.
The value of HIRD may be changed only when HACT = 0.
HIRD is ignored when not in a Universal Bus mode (HM ≠ $2 or $3).
Hardware and software resets clear HIRD.
Each of the bits HDSM, HRWP, HTAP, HDRP, HRSP, HIRH, and HIRD affect
Note:
the host port signals directly. To assure proper operation, these signals may be
changed only when HACT = 0. The HM2-HM0 bits must not be changed
together with these bits (i.e. in the same core write).
6-16 DSP56305 User's Manual MOTOROLA