Table of Contents
Advertisement
13.5.4.12
Internal Reserved Bits—VCRB Bits 4, 7
These bits are reserved for internal use and should be written with zero for proper
operation.
13.5.5
Viterbi Status Register (VSTR)
The Viterbi Status Register (VSTR) is a 16-bit read-only status register used by the
DSP56300 core to examine VCOP status and flags. All VSTR bits are cleared following
hardware, software, or VCOP individual reset. All the VSTR bits except OPC are also
cleared when VCOP is in the Idle state.
15
14
13
Reserved bit, Read as zero.
13.5.5.1
Initialize Flag (INIT)—VSTR Bit 0
The Initialize Flag (INIT) bit, when set, indicates the VCOP is being initialized. At
initialization the metric RAM is initialized with the start-up values (equal for all states or
a preferred starting state). Initialization lasts a period of time equal to the time required
for a single pass over all trellis states (i.e. a one-stage period), and is thus dependent
upon the number of states in the given code. This bit is cleared when initialization is
complete.
13.5.5.2
Flush Flag (FLSH)—VSTR Bit 1
The Flush Flag (FLSH) bit, when set, indicates the VCOP is performing a flush operation.
It is cleared when the flush operation is complete.
13.5.5.3
Operation Complete (OPC)—VSTR Bit 4
The Operation Complete (OPC) flag bit, when set, indicates the VCOP has completed its
operation and all the processed data block has been read out. The OPC bit indicates that
the VCOP is ready to start processing a new data block. It is cleared when any one of the
five enable bits (MAEN, DECEN, ENCEN, EQEN, and FLEN) is set. When OPC and
OCIE are set, an interrupt request is generated and OPC is cleared upon servicing that
interrupt request. This bit is disabled when CME (VCRB Bit 3) is set.
MOTOROLA
12
11
10
9
DOBF DREQ ESTG DRDY DONE OPC
Figure 13-11 Viterbi Status Register (VSTR)
DSP56305 User's Manual
8
7
6
5
VITERBI CO-PROCESSOR
Programming Model
4
3
2
1
FLSH
INIT
0
AA1320
13-23
Advertisement
Chapters
Table of Contents
