Motorola DSP56305 User Manual page 236

HOST INTERFACE (HI32)
HOST SIDE Programming Model
6.6.12 Interrupt Line - Interrupt Signal Configuration Register (CILP)
31 30 29 28
ML7 ML6 ML5 ML4
15 14 13 12
IP7 IP6 IP5 IP4
Hardwired to zero
Interrupt Line
Interrupt Signal
MIN_GNT
MAX_LAT
The CILP is a PCI standard 32-bit read-only register mapped into the PCI configuration
space, when in the PCI mode or in mode 0 (HM=$1 or $0). CILP is accessed if a
configuration read command is in progress and the PCI address is $FC. The CILP
register cannot be accessed by the DSP56300 core.
ML7-ML0: MAX_LAT is used for specifying how often the device needs to gain access to
the PCI bus. As the HI32 has no major requirements for the settings of Latency Timers,
these bits are hardwired to zero.
MG7-MG0: MIN_GNT is used for specifying how long a burst the device needs. As the
HI32 has no major requirements for the settings of Latency Timers, these bits are
hardwired to zero.
IP7-IP0: The Interrupt Signal bits specify which interrupt the device uses. A value of 1
corresponds to PCI INTA.
6-88
27 26 25 24
ML3 ML2 ML1 ML0
11 10 9 8
IP3 IP2 IP1 IP0
Bit
7-0 IL7-IL0
15-8 IP7-IP0
23-16 MG7-MG0
31-24 ML7-ML0
DSP56305 User's Manual
23 22 21 20
MG7 MG6 MG5 MG4
7 6 5 4
IL7 IL6 IL5 IL4
Hardwired to one
Value
Name
(hardwired)
---
$01
$00
$00
19 18 17 16
MG3 MG2 MG1 MG0
3 2 1 0
IL3 IL2 IL1 IL0
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