Hi32 Features In Universal Bus Modes - Motorola DSP56305 User Manual

HOST INTERFACE (HI32)
HI32 Features
• Supports a self configuration mode, for initialization of the configuration registers
in a system without an external system configurator
• Supports software driven PCI Interrupt Requests (Interrupt A).
• Generates vectored DSP56300 core interrupts — separately for receive, transmit,
transaction termination, error events and host commands
• Supports both 3.3 V and 5 V PCI signaling environments
• Supports address insertion in the data written to the HI32 by the host
• Supports parity generation, detection and reporting
• Supports system error generation and reporting
• Supports PCI Plug and Play
6.2.4

HI32 Features in Universal Bus Modes

• Operates as a slave in many standard bus environments (e.g. ISA bus or
DSP56300 core based DSP Port A bus)
• Transfers data at three clock cycles per transfer (i.e. 22 Mword/sec for a 66 MHz
DSP clock), when operating synchronously with a DSP56300 core–based DSP host
(two wait states per access)
• Supports high speed (fast peripheral) DSP56300 core DMA transfers (two core
clock cycles per DMA transfer)
• Supports words of 8,16, and 24 bits
• Supports output data alignment of 24-bit words to 16-bit words (two most
significant bytes, two least significant bytes)
• Supports input data alignment of 16-bit words to 24-bit words (left aligned and
zero filled, right aligned and zero extended, right aligned and sign extended)
• Supports an external data buffer for drive and voltage level compatibility with the
external bus (e.g. ISA bus)
• Generates interrupt requests: hardware driven (HIRQ) and software driven
(HINTA)
• Generates vectored DSP56300 core interrupts separately for receive and transmit
events and host commands
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