Once Breakpoint Control Register (Obcr); Figure 10-7 Once Breakpoint Control Register (Obcr); Bits 0–1; Bits 2–3 - Motorola DSP56305 User Manual

On-Chip Emulation Module
OnCE Memory Breakpoint Logic
10.5.6

OnCE Breakpoint Control Register (OBCR)

The OnCE Breakpoint Control Register (OBCR) is a 16-bit register used to define the
memory breakpoint events. OBCR can be read or written through the JTAG port. All the
bits of the OBCR are cleared on hardware reset. The OBCR is described in Figure 10-7.
15
OnCE Breakpoint
Control Register
*
Reset = $0010
Read/Write
* Indicates reserved bits, written as 0 for future compatibility

Figure 10-7 OnCE Breakpoint Control Register (OBCR)

10.5.6.1 Memory Breakpoint Select (MBS0–MBS1) Bits 0–1
The Memory Breakpoint Select bits (MBS0–MBS1) enable memory breakpoints 0 and 1,
allowing them to occur when a memory access is performed on P, X, or Y space. See
Table 10-6 for the definition of the MBS0–MBS1 bits.

Table 10-6 Memory Breakpoint 0 and 1 Select Table

MBS1 MBS0
0 0
0 1
1 0
1 1
10.5.6.2 Breakpoint 0 Read/Write Select (RW00–RW01) Bits 2–3
The Breakpoint 0 Read/Write Select bits (RW00–RW01) define the memory breakpoints
0 to occur when a memory address accesses is performed for read, write or both. See
Table 10-7 for the definition of the RW00–RW01 bits.
10-12
14 13 12 11 10
* * *
BT1 BT0
Reserved
Breakpoint on P access
Breakpoint on X access
Breakpoint on Y access
DSP56305 User's Manual
9 8 7 6 5
CC CC RW RW CC
11 10 11 10 01
Description
4 3 2 1 0
CC RW RW MB MB
00 01 00 S1 S0
AA0707
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