Table 6-4 Hi32 Modes; Hi32 Mode (Hm2-Hm0) Bits 22-20; Terminate And Reset (Hm[2:0] = 000) - Motorola DSP56305 User Manual

6.5.1.13

HI32 Mode (HM2-HM0) Bits 22-20

The HM bits control the operation modes and signal functionality of the HI32 (see
Table 6-4). The host port signals in the different modes are shown in Table 6-5.
6.5.1.13.1

Terminate and Reset (HM[2:0] = 000)

If the HI32 was in the PCI mode (HM[2:0] = 001), as an active PCI master: the HI32
generates a master initiated termination; if a selected target in a memory space
transaction, the HI32 generates a target-disconnect-C/retry event, thus completing the
PCI transaction. When the PCI idle state is subsequently detected, the HI32 clears HACT
in the DSR and enters the personal software (PS) reset state. In the personal software
reset state all data paths are cleared, and the HI32 will respond to all memory space
transactions with a retry event.
If the HI32 was not an active target in the PCI mode (HM[2:0]≠001) memory space
transaction, the HI32 immediately clears HACT in the DSR and enters the personal
software (PS) reset state.
Configuration space transactions are affected by clearing the HM bits. CSID must be
loaded, due to self configuration mode before the host can configure the DSP56305.
In the personal software reset the HI32 consumes very little current. This is a low-power
state. For even greater power saving, the HI32 may be programmed to the GPIO mode.
MOTOROLA

Table 6-4 HI32 Modes

HM[2:0]
000
001
010
011
100
101
110
111
DSP56305 User's Manual
DSP SIDE Programming Model
HI32 Mode
Terminate and Reset
PCI
Universal Bus
Enhanced Universal Bus
GPIO
Self Configuration
reserved
reserved
HOST INTERFACE (HI32)
6-17