Receive Buffer Lock Enable (Rble) Bit 20 - Motorola DSP56305 User Manual

HOST INTERFACE (HI32)
DSP SIDE Programming Model
6.5.2.13

Receive Buffer Lock Enable (RBLE) Bit 20

The RBLE bit is used, in the PCI mode (HM = $1), to ensure that the host-to-DSP data
path contains data from only one external master at any time. This is accomplished by
inhibiting the HI32 from responding to new PCI write transactions to the HTXR until the
DSP56300 core has read all the data written to the HTXR in the last access.
With RBLE set: After a non-exclusive write transaction to the HTXR, or upon HLOCK
negation after completion of an exclusive write access to the HTXR; or after the
completion of a read transaction initiated by the HI32:
– Forthcoming PCI write accesses to the HTXR will be disconnected (retry or
disconnect-C) until the DSP56300 core writes one to the host data transfer
complete (HDTC) bit in the DPSR.
– If the host-to-DSP data path is empty (SRRQ = 0 and MRRQ = 0), due to
DSP56300 core reads from the DRXR, the HDTC bit will be set. The HI32 will
disconnect (retry or disconnect-C) all PCI write accesses to the HTXR until the
DSP56300 core writes one to the HDTC bit to clear it.
If RBLE is cleared the HI32 will not set the HDTC bit.
If the HDTC bit is cleared the HI32 will respond to write PCI transactions according to
the status of the host-to-DSP data path.
RBLE is ignored when the HI32 is not in the PCI mode (HM≠$1).
The value of RBLE may be changed only when HACT = 0 or HDTC = 1.
Hardware and software resets clear RBLE.
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