Motorola DSP56305 User Manual page 85

24-bit digital signal processor
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Signal Name
Type
HAD16–
Input/
HAD31
Output
HD8–HD23
Input/
Output
HRST
Input
HRST
Input
HINTA
Output,
open
drain
MOTOROLA
Table 2-10 Host Interface (Continued)
State
During
Reset
Tri-stated
Host Address/Data 16–31—When the HI32 is
programmed to interface a PCI bus and the HI
function is selected, these signals are lines 16–31 of
the bidirectional, multiplexed Address/Data bus.
Host Data 8–23—When HI32 is programmed to
interface a universal non-PCI bus and the HI
function is selected, these signals are lines 8–23 of
the bidirectional Data bus.
Port B—When the HI32 is configured as GPIO
through the DCTR, these signals are internally
disconnected.
These inputs are 5 V tolerant.
Tri-stated
Hardware Reset—When the HI32 is programmed
to interface a PCI bus and the HI function is
selected, this is the Hardware Reset input.
Hardware Reset—When HI32 is programmed to
interface a universal non-PCI bus and the HI
function is selected, this signal is the Hardware
Reset Schmitt-trigger input.
Port B—When the HI32 is configured as GPIO
through the DCTR, this signal is internally
disconnected.
This input is 5 V tolerant.
Tri-stated
Host Interrupt A—When the HI function is
selected, this signal is the Interrupt A open-drain
output.
Port B—When the HI32 is configured as GPIO
through the DCTR, this signal is internally
disconnected.
This input is 5 V tolerant.
DSP56305 User's Manual
Signal/Connection Descriptions
Host Interface (HI32)
Signal Description
2-27

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