Table 2-8 External Bus Control Signals - Motorola DSP56305 User Manual

2.6.3 External Bus Control
Signal
Type
Name
AA0–AA/ Output
RAS0–
RAS3
RD Output
WR Output
BS Output
MOTOROLA

Table 2-8 External Bus Control Signals

State During
Reset, Wait,
or Stop
Tri-stated Address Attribute or Row Address Strobe—When
defined as AA, these signals can be used as chip selects
or additional address lines.
When defined as RAS, these signals can be used as
RAS for Dynamic Random Access Memory (DRAM)
interface. These signals have programmable polarity.
Tri-stated Read Enable—When the DSP is the bus master, RD is
asserted to read external memory on the data bus
(D0–D23). Otherwise, RD is tri-stated.
Tri-stated Write Enable—When the DSP is the bus master, WR is
asserted to write external memory on the data bus
(D0–D23). Otherwise, the signals are tri-stated.
Tri-stated Bus Strobe—When the DSP is the bus master, BS is
asserted for half a clock cycle at the start of a bus cycle
to provide an "early bus start" signal for a bus
controller. If the external bus is not used during an
instruction cycle, BS remains deasserted until the next
external bus cycle.
DSP56305 User's Manual
Signal/Connection Descriptions
External Memory Expansion Port (Port A)
Signal Description
2-11