Ccop Data Fifo Register (Cdfr) - Motorola DSP56305 User Manual

CYCLIC CODE CO-PROCESSOR
CCOP Programming Model
$10
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$13
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$1A
$1B
$1C
$1D
$1E
14.4.1

CCOP Data FIFO Register (CDFR)

The CCOP Data FIFO Register (CDFR) is a 24-bit read/write 5-word deep FIFO register
used to store input and output data during the CCOP processing. When CCOP is in the
Idle state or in the input phase, CDFR operates as an input data FIFO, and expects data
from the DSP56300 core for processing. To load it, up to five successive writes to the
same memory location should be executed. If less than 120 bits are to be processed, the
value of the unused bits is disregarded.
Data is clocked from the CDFR into the any or all of the CFSRs under the control of the
Input Counter of the CCNT (IC[7:0], CCNT bits 0–7). They are shifted in Least
Significant Bit (LSB) first.
14-8
Table 14-1 CCOP Programming Model
CCOP Linear FeedBack Shift Register B
CCOP FeedBack Tap Register B
CCOP FeedForward Tap Register B
CCOP Bit Select Register B
CCOP Mask Register B
CCOP Linear FeedBack Shift Register C
CCOP FeedBack Tap Register C
CCOP FeedForward Tap Register C
CCOP Bit Select Register C
CCOP Mask Register C
CCOP Linear FeedBack Shift Register D
CCOP FeedBack Tap Register D
CCOP FeedForward Tap Register D
CCOP Bit Select Register D
CCOP Mask Register D
DSP56305 User's Manual
CFSRB
CFBTB
CFFTB
CBSRB
CMSKB
CFSRC
CFBTC
CFFTC
CBSRC
CMSKC
CFSRD
CFBTD
CFFTD
CBSRD
CMSKD
MOTOROLA