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Signal Processors
DSP56600
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Motorola DSP56600 Manual
Application optimization for digital signal processors
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Contents
Table of Contents
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Table of Contents
Table of Contents
Section 1 Introduction
Dsp56300 Core Family
Dsp56600 Core Family
Enhancements over the Dsp56000
Instruction Set Enhancements
Table 1-1 New Instructions in DSP56300 and
Architectural Enhancements
Application Note Structure
DSP56300 and DSP56600 Features Description and Use
Optimizing the Code for Best Performance 1-7 1.4.3
Appendixes
Section 2 Data Operations
Using the Dual Data Paths
Table 2-1 Parallel Move Instructions
Table 2-2 Registers Used in Parallel XY Moves
Table 2-3 Registers Used in Long Addressing
16-Bit Arithmetic Mode (Dsp56300 Only)
The Max Instruction
Using the Barrel Shifter
Table 2-4 Data Operations Using Multi-Shift
Figure 2-1 the Fast Normalization Operation for the DSP56300
Bit Manipulation Instructions
Table 2-5 Bit Manipulation Instructions
Double Precision Arithmetic
Figure 2-2 48 × 48-Bit Multiplication with 48 Bits of the Result
Kept
Using Less Straight-Forward Instructions
Section 3 Program Control
Hardware Loops
The Hardware Stack
Table 3-1 Implicit Stack Activity
Figure 3-1 State of the Stack When IRQA Is Serviced
Using the Stack Extension
Table 3-2 Registers Involved in Stack Extension
Table 3-3 Stack Status Information
Task Switching with the Stack Extension
Conditional Dalu Instructions
Table 3-4 Options for Parallel Moves and Conditional
Pc Relative Instructions
Table 3-5 Instructions with Program Memory
Arguments
Using Fast Interrupts
Using the Dma
Introduction
Conserving Core Mips by Working in Parallel
Using Slow, Low-Cost Memories
Servicing a Peripheral
Figure 4-1 DMA Addressing Modes for SCI
Transmitters
Data Transfer Optimization Hints
Instruction Cache and Memory Features
The Instruction Cache
Table 5-1 Example for Cycle Count with Cache Enabled Versus Disabled
Cache Sectors
Control of Sector Allocation
Cache Burst Mode
Table 5-2 Cycle Count Example with and Without
Burst Mode
Memory Switch
Figure 5-1 DSP56302 Memory Maps
Using the Bootstrap Rom
Pipeline Interlocks
Data Alu Pipeline Interlocks
Section 6 Pipeline Interlocks
What Are the Data ALU Pipeline Interlocks
Avoiding Data ALU Pipeline Interlocks
Code Reorder
Loop Unrolling
Loop Unrolling in N Array Scale Routine
Unrolling in Memory Array Copy Routine
Saving Interlocks by Using the TFR Instruction
Address Generation Pipeline Interlocks
What Are the Address Generation Pipeline Interlocks
Avoiding Address Generation Pipeline Interlocks
Stack Extension Delays
Stack Extension Full/Empty Cases
Avoiding Stack Extension Delays
Program Flow-Control Pipeline Interlocks
What Are the Program Flow-Control Pipeline Interlocks
MOVE to the Status Register (SR)
MOVE to the System Stack High/Low (SSH/SSL)
JMP to Last Addresses of a Do-Loop (la or LA-1)
RTI to Last Addresses of a Do-Loop (la or LA-1)
MOVE from the System Stack High (SSH)
Conditional Instructions
Avoiding Program Flow-Control Pipeline Interlocks
Section 7 Compact Opcode Use
Cycle Count of an Instruction
Opening Small REP and DO Loops
Replacing Jumps with Conditional Execution
Instructions
Inverting Condition in Conditional Jump Instructions
Addressing Modes
Single Cycle Addressing Modes
Execution
Short Addressing Mode
Short Immediate Mode
Short Immediate Operands
Register Addressing
Word Count
Peripheral Addressing
Special Instructions
Dual Data Spaces
Using the TFR Instructions
Clearing Registers
Appendix A Saving Power
A.1 Low Power Modes
Wait Standby Mode
Appendix A Saving Power
Low-Power Clock Divider
Stop Standby Mode
A.2 Disabling Functional Blocks
Appendix B Debug and Test Support
Appendix B Debug and Test Support
B.1 Once PORT FEATURES
B.2 Jtag Port Features
B.3 Address Tracing
Appendix C Using the Profiler
Appendix C Using the Profiler
C.1 Scope
C.2 Creating a Profiler
C.3 the Profiling Report
Basic Report
Symbol Report
C.3.2 Symbol Report
Code Coverage Report
Basic Subroutine Report
Subroutine Call Graph Report
Subroutine Dependency Report
Subroutine Call Report
C.4 Using the Profile Report
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M o t o r o l a ' s
H i g h - P e r f o r m a n c e
DSP56300/DSP56600
Digital Signal
Processors
Application
Optimization
for the
D S P
T e c h n o l o g y
APR20/D
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