Motorola DSP56305 User Manual page 23

13.5.8.1 Tap Vector D (TAPD{4:0])-VTPB Bits 4-0 . . . . . . . . . 13-26
13.5.8.2 Tap Vector E (TAPE[4:0])-VTPB Bits 9-5 . . . . . . . . . 13-26
13.5.8.3 Tap Vector F (TAPF[4:0])-VTPB Bits 14-10. . . . . . . . 13-26
13.5.8.4 Reserved Bit-VTPB Bit 15 . . . . . . . . . . . . . . . . . . . . . 13-26
13.5.9 Viterbi Trellis Setup Register (VTSR) . . . . . . . . . . . . . . . . 13-27
13.5.9.1 Initial State (IS[5:0])-VTSR Bits 5-0 . . . . . . . . . . . . . . 13-27
13.5.9.2 End State (ES[5:0])-VTSR Bits 13-8 . . . . . . . . . . . . . 13-27
13.5.9.3 Reserved Bits-VTSR Bits 6, 7, 14, 15. . . . . . . . . . . . . 13-27
13.5.10 Viterbi Bit Error Rate Register/Counter (VBER) . . . . . . . . 13-27
13.5.11 Viterbi WED Setup Register (VWES) . . . . . . . . . . . . . . . . 13-28
13.5.11.1 Window Start Location (WSTR[7:0])-
VWES Bits 7-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-29
13.5.11.2 Window Length (WLEN[7:0])-VWES Bits 15-8 . . . . . 13-29
13.5.12 Viterbi WED Data Register (VWED) . . . . . . . . . . . . . . . . . 13-29
13.5.13 Viterbi Memory Access Register (VMEM) . . . . . . . . . . . . . 13-29
13.6 CHIP DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-30
13.6.1 Memory description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-30
13.6.2 Interrupt and DMA Sources . . . . . . . . . . . . . . . . . . . . . . . . 13-31
13.6.3 I/O Register and Related Interrupts for Different Modes . . 13-31
13.6.4 Soft Decision Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-32
13.7 VITERBI BUTTERFLY IMPLEMENTATION. . . . . . . . . . . . . . 13-33
13.8 PERFORMANCE ANALYSIS . . . . . . . . . . . . . . . . . . . . . . . . . 13-34
13.9 PROGRAMMING EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . 13-37
13.9.1 Channel Encode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-37
13.9.2 Channel Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-40
13.9.3 Channel Equalization with DMA
including Read/Write Memory Access . . . . . . . . . . . . . . . . 13-45
13.10 REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-51
SECTION 14 CYCLIC CODE CO-PROCESSOR . . . . . . . . . . . . . . 14-1
14.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
14.2 KEY FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
14.3 CCOP BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
14.3.1 Cipher Mode Register Configuration . . . . . . . . . . . . . . . . . . 14-4
14.3.2 Parity Coding Modes Register Configuration. . . . . . . . . . . . 14-5
14.4 CCOP PROGRAMMING MODEL . . . . . . . . . . . . . . . . . . . . . . 14-6
MOTOROLA DSP56305 User's Manual xxi